Lines Matching full:bus
38 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) in aspeed_i2c_bus_raise_interrupt() argument
40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_interrupt()
41 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_raise_interrupt()
42 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); in aspeed_i2c_bus_raise_interrupt()
43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | in aspeed_i2c_bus_raise_interrupt()
49 aspeed_i2c_bus_pkt_mode_en(bus) && in aspeed_i2c_bus_raise_interrupt()
50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? in aspeed_i2c_bus_raise_interrupt()
52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? in aspeed_i2c_bus_raise_interrupt()
54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? in aspeed_i2c_bus_raise_interrupt()
56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? in aspeed_i2c_bus_raise_interrupt()
58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? in aspeed_i2c_bus_raise_interrupt()
60 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? in aspeed_i2c_bus_raise_interrupt()
62 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? in aspeed_i2c_bus_raise_interrupt()
65 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf); in aspeed_i2c_bus_raise_interrupt()
68 raise_irq = bus->regs[reg_intr_sts] & intr_ctrl_mask ; in aspeed_i2c_bus_raise_interrupt()
71 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_raise_interrupt()
72 bus->regs[reg_intr_sts] &= intr_ctrl_mask; in aspeed_i2c_bus_raise_interrupt()
76 bus->controller->intr_status |= 1 << bus->id; in aspeed_i2c_bus_raise_interrupt()
77 qemu_irq_raise(aic->bus_get_irq(bus)); in aspeed_i2c_bus_raise_interrupt()
81 static inline void aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus *bus) in aspeed_i2c_bus_raise_slave_interrupt() argument
83 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_slave_interrupt()
85 if (!bus->regs[R_I2CS_INTR_STS]) { in aspeed_i2c_bus_raise_slave_interrupt()
89 bus->controller->intr_status |= 1 << bus->id; in aspeed_i2c_bus_raise_slave_interrupt()
90 qemu_irq_raise(aic->bus_get_irq(bus)); in aspeed_i2c_bus_raise_slave_interrupt()
93 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, in aspeed_i2c_bus_old_read() argument
96 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_old_read()
97 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; in aspeed_i2c_bus_old_read()
111 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); in aspeed_i2c_bus_old_read()
120 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_old_read()
136 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); in aspeed_i2c_bus_old_read()
140 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, in aspeed_i2c_bus_new_read() argument
143 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_new_read()
144 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; in aspeed_i2c_bus_new_read()
167 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_new_read()
172 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); in aspeed_i2c_bus_new_read()
191 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); in aspeed_i2c_bus_new_read()
198 AspeedI2CBus *bus = opaque; in aspeed_i2c_bus_read() local
199 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_read()
200 return aspeed_i2c_bus_new_read(bus, offset, size); in aspeed_i2c_bus_read()
202 return aspeed_i2c_bus_old_read(bus, offset, size); in aspeed_i2c_bus_read()
205 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) in aspeed_i2c_set_state() argument
207 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_set_state()
208 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, in aspeed_i2c_set_state()
211 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); in aspeed_i2c_set_state()
215 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) in aspeed_i2c_get_state() argument
217 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_get_state()
218 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, in aspeed_i2c_get_state()
221 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); in aspeed_i2c_get_state()
224 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) in aspeed_i2c_dma_read() argument
227 AspeedI2CState *s = bus->controller; in aspeed_i2c_dma_read()
228 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); in aspeed_i2c_dma_read()
230 result = address_space_read(&s->dram_as, bus->dma_dram_offset, in aspeed_i2c_dma_read()
235 __func__, bus->dma_dram_offset); in aspeed_i2c_dma_read()
239 bus->dma_dram_offset++; in aspeed_i2c_dma_read()
240 bus->regs[reg_dma_len]--; in aspeed_i2c_dma_read()
244 static int aspeed_i2c_bus_send(AspeedI2CBus *bus) in aspeed_i2c_bus_send() argument
246 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_send()
249 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_bus_send()
250 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); in aspeed_i2c_bus_send()
251 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); in aspeed_i2c_bus_send()
252 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); in aspeed_i2c_bus_send()
253 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, in aspeed_i2c_bus_send()
256 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { in aspeed_i2c_bus_send()
258 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_bus_send()
262 ret = i2c_send(bus->bus, pool_base[i]); in aspeed_i2c_bus_send()
267 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); in aspeed_i2c_bus_send()
268 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { in aspeed_i2c_bus_send()
270 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_send()
271 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); in aspeed_i2c_bus_send()
273 while (bus->regs[reg_dma_len]) { in aspeed_i2c_bus_send()
275 aspeed_i2c_dma_read(bus, &data); in aspeed_i2c_bus_send()
276 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], in aspeed_i2c_bus_send()
277 bus->regs[reg_dma_len], data); in aspeed_i2c_bus_send()
278 ret = i2c_send(bus->bus, data); in aspeed_i2c_bus_send()
283 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_send()
284 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, in aspeed_i2c_bus_send()
285 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, in aspeed_i2c_bus_send()
289 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); in aspeed_i2c_bus_send()
292 bus->regs[reg_byte_buf]); in aspeed_i2c_bus_send()
293 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); in aspeed_i2c_bus_send()
299 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) in aspeed_i2c_bus_recv() argument
301 AspeedI2CState *s = bus->controller; in aspeed_i2c_bus_recv()
305 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_bus_recv()
306 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); in aspeed_i2c_bus_recv()
307 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); in aspeed_i2c_bus_recv()
308 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); in aspeed_i2c_bus_recv()
309 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, in aspeed_i2c_bus_recv()
312 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { in aspeed_i2c_bus_recv()
313 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_bus_recv()
314 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, in aspeed_i2c_bus_recv()
320 pool_base[i] = i2c_recv(bus->bus); in aspeed_i2c_bus_recv()
326 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); in aspeed_i2c_bus_recv()
327 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); in aspeed_i2c_bus_recv()
328 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { in aspeed_i2c_bus_recv()
330 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_recv()
331 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_recv()
334 while (bus->regs[reg_dma_len]) { in aspeed_i2c_bus_recv()
337 data = i2c_recv(bus->bus); in aspeed_i2c_bus_recv()
338 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], in aspeed_i2c_bus_recv()
339 bus->regs[reg_dma_len], data); in aspeed_i2c_bus_recv()
341 result = address_space_write(&s->dram_as, bus->dma_dram_offset, in aspeed_i2c_bus_recv()
346 __func__, bus->dma_dram_offset); in aspeed_i2c_bus_recv()
350 bus->dma_dram_offset++; in aspeed_i2c_bus_recv()
351 bus->regs[reg_dma_len]--; in aspeed_i2c_bus_recv()
353 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_recv()
354 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, in aspeed_i2c_bus_recv()
355 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, in aspeed_i2c_bus_recv()
359 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); in aspeed_i2c_bus_recv()
361 data = i2c_recv(bus->bus); in aspeed_i2c_bus_recv()
362 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); in aspeed_i2c_bus_recv()
363 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); in aspeed_i2c_bus_recv()
367 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) in aspeed_i2c_handle_rx_cmd() argument
369 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_handle_rx_cmd()
370 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_handle_rx_cmd()
372 aspeed_i2c_set_state(bus, I2CD_MRXD); in aspeed_i2c_handle_rx_cmd()
373 aspeed_i2c_bus_recv(bus); in aspeed_i2c_handle_rx_cmd()
374 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); in aspeed_i2c_handle_rx_cmd()
375 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { in aspeed_i2c_handle_rx_cmd()
376 i2c_nack(bus->bus); in aspeed_i2c_handle_rx_cmd()
378 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); in aspeed_i2c_handle_rx_cmd()
379 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); in aspeed_i2c_handle_rx_cmd()
380 aspeed_i2c_set_state(bus, I2CD_MACTIVE); in aspeed_i2c_handle_rx_cmd()
383 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) in aspeed_i2c_get_addr() argument
385 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_get_addr()
386 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); in aspeed_i2c_get_addr()
387 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_get_addr()
389 if (aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_get_addr()
390 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | in aspeed_i2c_get_addr()
391 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); in aspeed_i2c_get_addr()
393 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { in aspeed_i2c_get_addr()
394 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_get_addr()
397 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { in aspeed_i2c_get_addr()
400 aspeed_i2c_dma_read(bus, &data); in aspeed_i2c_get_addr()
403 return bus->regs[reg_byte_buf]; in aspeed_i2c_get_addr()
407 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) in aspeed_i2c_check_sram() argument
409 AspeedI2CState *s = bus->controller; in aspeed_i2c_check_sram()
411 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_check_sram()
412 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || in aspeed_i2c_check_sram()
413 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || in aspeed_i2c_check_sram()
414 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || in aspeed_i2c_check_sram()
415 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); in aspeed_i2c_check_sram()
432 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) in aspeed_i2c_bus_cmd_dump() argument
436 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_bus_cmd_dump()
437 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); in aspeed_i2c_bus_cmd_dump()
438 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_cmd_dump()
439 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); in aspeed_i2c_bus_cmd_dump()
440 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { in aspeed_i2c_bus_cmd_dump()
441 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 1; in aspeed_i2c_bus_cmd_dump()
442 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { in aspeed_i2c_bus_cmd_dump()
443 count = bus->regs[reg_dma_len]; in aspeed_i2c_bus_cmd_dump()
449 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", in aspeed_i2c_bus_cmd_dump()
450 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", in aspeed_i2c_bus_cmd_dump()
451 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", in aspeed_i2c_bus_cmd_dump()
452 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", in aspeed_i2c_bus_cmd_dump()
453 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", in aspeed_i2c_bus_cmd_dump()
454 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", in aspeed_i2c_bus_cmd_dump()
455 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", in aspeed_i2c_bus_cmd_dump()
456 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", in aspeed_i2c_bus_cmd_dump()
457 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); in aspeed_i2c_bus_cmd_dump()
459 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, in aspeed_i2c_bus_cmd_dump()
460 bus->regs[reg_intr_sts]); in aspeed_i2c_bus_cmd_dump()
467 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) in aspeed_i2c_bus_handle_cmd() argument
469 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_handle_cmd()
470 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); in aspeed_i2c_bus_handle_cmd()
471 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); in aspeed_i2c_bus_handle_cmd()
473 if (!aspeed_i2c_check_sram(bus)) { in aspeed_i2c_bus_handle_cmd()
478 aspeed_i2c_bus_cmd_dump(bus); in aspeed_i2c_bus_handle_cmd()
481 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { in aspeed_i2c_bus_handle_cmd()
482 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? in aspeed_i2c_bus_handle_cmd()
486 aspeed_i2c_set_state(bus, state); in aspeed_i2c_bus_handle_cmd()
488 addr = aspeed_i2c_get_addr(bus); in aspeed_i2c_bus_handle_cmd()
489 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), in aspeed_i2c_bus_handle_cmd()
491 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); in aspeed_i2c_bus_handle_cmd()
492 if (aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_handle_cmd()
493 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
497 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_handle_cmd()
498 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); in aspeed_i2c_bus_handle_cmd()
502 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); in aspeed_i2c_bus_handle_cmd()
504 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { in aspeed_i2c_bus_handle_cmd()
505 if (bus->regs[reg_dma_len] == 0) { in aspeed_i2c_bus_handle_cmd()
506 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
508 } else if (!SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { in aspeed_i2c_bus_handle_cmd()
509 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
513 if (!i2c_bus_busy(bus->bus)) { in aspeed_i2c_bus_handle_cmd()
514 if (aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_handle_cmd()
515 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
516 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_handle_cmd()
520 aspeed_i2c_set_state(bus, I2CD_MACTIVE); in aspeed_i2c_bus_handle_cmd()
523 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { in aspeed_i2c_bus_handle_cmd()
524 aspeed_i2c_set_state(bus, I2CD_MTXD); in aspeed_i2c_bus_handle_cmd()
525 if (aspeed_i2c_bus_send(bus)) { in aspeed_i2c_bus_handle_cmd()
526 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); in aspeed_i2c_bus_handle_cmd()
527 i2c_end_transfer(bus->bus); in aspeed_i2c_bus_handle_cmd()
529 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); in aspeed_i2c_bus_handle_cmd()
531 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
532 aspeed_i2c_set_state(bus, I2CD_MACTIVE); in aspeed_i2c_bus_handle_cmd()
535 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || in aspeed_i2c_bus_handle_cmd()
536 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && in aspeed_i2c_bus_handle_cmd()
537 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { in aspeed_i2c_bus_handle_cmd()
538 aspeed_i2c_handle_rx_cmd(bus); in aspeed_i2c_bus_handle_cmd()
541 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { in aspeed_i2c_bus_handle_cmd()
542 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { in aspeed_i2c_bus_handle_cmd()
544 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); in aspeed_i2c_bus_handle_cmd()
545 if (aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_handle_cmd()
546 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
549 aspeed_i2c_set_state(bus, I2CD_MSTOP); in aspeed_i2c_bus_handle_cmd()
550 i2c_end_transfer(bus->bus); in aspeed_i2c_bus_handle_cmd()
551 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); in aspeed_i2c_bus_handle_cmd()
553 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); in aspeed_i2c_bus_handle_cmd()
554 aspeed_i2c_set_state(bus, I2CD_IDLE); in aspeed_i2c_bus_handle_cmd()
556 i2c_schedule_pending_master(bus->bus); in aspeed_i2c_bus_handle_cmd()
559 if (aspeed_i2c_bus_pkt_mode_en(bus)) { in aspeed_i2c_bus_handle_cmd()
560 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_handle_cmd()
564 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, in aspeed_i2c_bus_new_write() argument
567 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_new_write()
571 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); in aspeed_i2c_bus_new_write()
575 bus->regs[R_I2CC_FUN_CTRL] = value; in aspeed_i2c_bus_new_write()
578 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; in aspeed_i2c_bus_new_write()
581 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, in aspeed_i2c_bus_new_write()
585 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; in aspeed_i2c_bus_new_write()
586 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); in aspeed_i2c_bus_new_write()
589 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; in aspeed_i2c_bus_new_write()
592 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) in aspeed_i2c_bus_new_write()
596 if (aspeed_i2c_bus_pkt_mode_en(bus) && in aspeed_i2c_bus_new_write()
598 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; in aspeed_i2c_bus_new_write()
599 if (!bus->regs[R_I2CM_INTR_STS]) { in aspeed_i2c_bus_new_write()
600 bus->controller->intr_status &= ~(1 << bus->id); in aspeed_i2c_bus_new_write()
601 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
603 aspeed_i2c_bus_raise_slave_interrupt(bus); in aspeed_i2c_bus_new_write()
606 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); in aspeed_i2c_bus_new_write()
607 if (!bus->regs[R_I2CM_INTR_STS]) { in aspeed_i2c_bus_new_write()
608 bus->controller->intr_status &= ~(1 << bus->id); in aspeed_i2c_bus_new_write()
609 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
611 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, in aspeed_i2c_bus_new_write()
613 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, in aspeed_i2c_bus_new_write()
615 aspeed_i2c_handle_rx_cmd(bus); in aspeed_i2c_bus_new_write()
616 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_new_write()
620 if (!aspeed_i2c_bus_is_enabled(bus)) { in aspeed_i2c_bus_new_write()
624 if (!aspeed_i2c_bus_is_master(bus)) { in aspeed_i2c_bus_new_write()
637 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { in aspeed_i2c_bus_new_write()
644 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { in aspeed_i2c_bus_new_write()
645 bus->regs[R_I2CM_CMD] |= value; in aspeed_i2c_bus_new_write()
647 bus->regs[R_I2CM_CMD] = value; in aspeed_i2c_bus_new_write()
650 aspeed_i2c_bus_handle_cmd(bus, value); in aspeed_i2c_bus_new_write()
651 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_new_write()
654 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, in aspeed_i2c_bus_new_write()
656 bus->dma_dram_offset = in aspeed_i2c_bus_new_write()
657 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_write()
659 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, in aspeed_i2c_bus_new_write()
663 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, in aspeed_i2c_bus_new_write()
665 bus->dma_dram_offset = in aspeed_i2c_bus_new_write()
666 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_write()
668 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, in aspeed_i2c_bus_new_write()
676 bus->regs[R_I2CM_DMA_LEN] = value; in aspeed_i2c_bus_new_write()
680 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, in aspeed_i2c_bus_new_write()
684 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, in aspeed_i2c_bus_new_write()
690 bus->regs[R_I2CM_DMA_LEN_STS] = 0; in aspeed_i2c_bus_new_write()
697 bus->regs[R_I2CS_DEV_ADDR] = value; in aspeed_i2c_bus_new_write()
700 bus->regs[R_I2CS_DMA_RX_ADDR] = value; in aspeed_i2c_bus_new_write()
705 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN, in aspeed_i2c_bus_new_write()
708 bus->regs[R_I2CS_DMA_LEN] = value; in aspeed_i2c_bus_new_write()
713 bus->regs[R_I2CS_CMD] |= value; in aspeed_i2c_bus_new_write()
715 bus->regs[R_I2CS_CMD] = value; in aspeed_i2c_bus_new_write()
717 i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]); in aspeed_i2c_bus_new_write()
720 bus->regs[R_I2CS_INTR_CTRL] = value; in aspeed_i2c_bus_new_write()
724 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) { in aspeed_i2c_bus_new_write()
725 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) && in aspeed_i2c_bus_new_write()
727 bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000; in aspeed_i2c_bus_new_write()
730 bus->regs[R_I2CS_INTR_STS] &= ~value; in aspeed_i2c_bus_new_write()
732 if (!bus->regs[R_I2CS_INTR_STS]) { in aspeed_i2c_bus_new_write()
733 bus->controller->intr_status &= ~(1 << bus->id); in aspeed_i2c_bus_new_write()
734 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
736 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_new_write()
739 bus->regs[R_I2CS_DMA_LEN_STS] = 0; in aspeed_i2c_bus_new_write()
760 bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value, in aspeed_i2c_bus_new_write()
763 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, in aspeed_i2c_bus_new_write()
772 bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value, in aspeed_i2c_bus_new_write()
775 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, in aspeed_i2c_bus_new_write()
789 bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value, in aspeed_i2c_bus_new_write()
792 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, in aspeed_i2c_bus_new_write()
801 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, in aspeed_i2c_bus_old_write() argument
804 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_old_write()
807 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); in aspeed_i2c_bus_old_write()
812 i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]); in aspeed_i2c_bus_old_write()
814 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; in aspeed_i2c_bus_old_write()
817 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; in aspeed_i2c_bus_old_write()
820 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; in aspeed_i2c_bus_old_write()
823 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; in aspeed_i2c_bus_old_write()
826 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) in aspeed_i2c_bus_old_write()
828 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); in aspeed_i2c_bus_old_write()
829 if (!bus->regs[R_I2CD_INTR_STS]) { in aspeed_i2c_bus_old_write()
830 bus->controller->intr_status &= ~(1 << bus->id); in aspeed_i2c_bus_old_write()
831 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_old_write()
834 if (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, M_RX_CMD) || in aspeed_i2c_bus_old_write()
835 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, in aspeed_i2c_bus_old_write()
837 aspeed_i2c_handle_rx_cmd(bus); in aspeed_i2c_bus_old_write()
838 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_old_write()
839 } else if (aspeed_i2c_get_state(bus) == I2CD_STXD) { in aspeed_i2c_bus_old_write()
840 i2c_ack(bus->bus); in aspeed_i2c_bus_old_write()
845 bus->regs[R_I2CD_DEV_ADDR] = value; in aspeed_i2c_bus_old_write()
848 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; in aspeed_i2c_bus_old_write()
849 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); in aspeed_i2c_bus_old_write()
853 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); in aspeed_i2c_bus_old_write()
856 if (!aspeed_i2c_bus_is_enabled(bus)) { in aspeed_i2c_bus_old_write()
860 if (!aspeed_i2c_bus_is_master(bus)) { in aspeed_i2c_bus_old_write()
873 bus->regs[R_I2CD_CMD] &= ~0xFFFF; in aspeed_i2c_bus_old_write()
874 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; in aspeed_i2c_bus_old_write()
876 aspeed_i2c_bus_handle_cmd(bus, value); in aspeed_i2c_bus_old_write()
877 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_old_write()
885 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_old_write()
895 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; in aspeed_i2c_bus_old_write()
896 if (!bus->regs[R_I2CD_DMA_LEN]) { in aspeed_i2c_bus_old_write()
910 AspeedI2CBus *bus = opaque; in aspeed_i2c_bus_write() local
911 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_write()
912 aspeed_i2c_bus_new_write(bus, offset, value, size); in aspeed_i2c_bus_write()
914 aspeed_i2c_bus_old_write(bus, offset, value, size); in aspeed_i2c_bus_write()
1092 object_initialize_child(obj, "bus[*]", &s->busses[i], in aspeed_i2c_instance_init()
1217 Object *bus = OBJECT(&s->busses[i]); in aspeed_i2c_realize() local
1220 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { in aspeed_i2c_realize()
1224 if (!object_property_set_uint(bus, "bus-id", i, errp)) { in aspeed_i2c_realize()
1228 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { in aspeed_i2c_realize()
1288 static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus, in aspeed_i2c_bus_new_slave_event() argument
1293 if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) { in aspeed_i2c_bus_new_slave_event()
1298 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_new_slave_event()
1299 bus->dma_dram_offset = in aspeed_i2c_bus_new_slave_event()
1300 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_slave_event()
1301 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR)); in aspeed_i2c_bus_new_slave_event()
1302 bus->regs[R_I2CC_DMA_LEN] = in aspeed_i2c_bus_new_slave_event()
1303 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1; in aspeed_i2c_bus_new_slave_event()
1304 i2c_ack(bus->bus); in aspeed_i2c_bus_new_slave_event()
1307 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_new_slave_event()
1308 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); in aspeed_i2c_bus_new_slave_event()
1309 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, NORMAL_STOP, 1); in aspeed_i2c_bus_new_slave_event()
1310 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, RX_DONE, 1); in aspeed_i2c_bus_new_slave_event()
1311 aspeed_i2c_bus_raise_slave_interrupt(bus); in aspeed_i2c_bus_new_slave_event()
1325 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); in aspeed_i2c_bus_slave_event() local
1326 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_slave_event()
1327 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); in aspeed_i2c_bus_slave_event()
1328 uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus); in aspeed_i2c_bus_slave_event()
1329 uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr, in aspeed_i2c_bus_slave_event()
1332 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_slave_event()
1333 return aspeed_i2c_bus_new_slave_event(bus, event); in aspeed_i2c_bus_slave_event()
1339 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1); in aspeed_i2c_bus_slave_event()
1341 ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); in aspeed_i2c_bus_slave_event()
1342 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); in aspeed_i2c_bus_slave_event()
1344 aspeed_i2c_set_state(bus, I2CD_STXD); in aspeed_i2c_bus_slave_event()
1349 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); in aspeed_i2c_bus_slave_event()
1351 aspeed_i2c_set_state(bus, I2CD_IDLE); in aspeed_i2c_bus_slave_event()
1359 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_slave_event()
1364 static void aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus *bus, uint8_t data) in aspeed_i2c_bus_new_slave_send_async() argument
1366 assert(address_space_write(&bus->controller->dram_as, in aspeed_i2c_bus_new_slave_send_async()
1367 bus->dma_dram_offset, in aspeed_i2c_bus_new_slave_send_async()
1370 bus->dma_dram_offset++; in aspeed_i2c_bus_new_slave_send_async()
1371 bus->regs[R_I2CC_DMA_LEN]--; in aspeed_i2c_bus_new_slave_send_async()
1372 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, in aspeed_i2c_bus_new_slave_send_async()
1373 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN) + 1); in aspeed_i2c_bus_new_slave_send_async()
1374 i2c_ack(bus->bus); in aspeed_i2c_bus_new_slave_send_async()
1380 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); in aspeed_i2c_bus_slave_send_async() local
1381 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_slave_send_async()
1382 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); in aspeed_i2c_bus_slave_send_async()
1384 if (aspeed_i2c_is_new_mode(bus->controller)) { in aspeed_i2c_bus_slave_send_async()
1385 return aspeed_i2c_bus_new_slave_send_async(bus, data); in aspeed_i2c_bus_slave_send_async()
1388 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); in aspeed_i2c_bus_slave_send_async()
1389 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); in aspeed_i2c_bus_slave_send_async()
1391 aspeed_i2c_bus_raise_interrupt(bus); in aspeed_i2c_bus_slave_send_async()
1399 dc->desc = "Aspeed I2C Bus Slave"; in aspeed_i2c_bus_slave_class_init()
1417 i2c_end_transfer(s->bus); in aspeed_i2c_bus_reset()
1436 s->bus = i2c_init_bus(dev, name); in aspeed_i2c_bus_realize()
1437 s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, in aspeed_i2c_bus_realize()
1450 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
1460 dc->desc = "Aspeed I2C Bus"; in aspeed_i2c_bus_class_init()
1473 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) in aspeed_2400_i2c_bus_get_irq() argument
1475 return bus->controller->irq; in aspeed_2400_i2c_bus_get_irq()
1478 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) in aspeed_2400_i2c_bus_pool_base() argument
1481 &bus->controller->share_pool[ARRAY_FIELD_EX32(bus->regs, in aspeed_2400_i2c_bus_pool_base()
1485 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; in aspeed_2400_i2c_bus_pool_base()
1512 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) in aspeed_2500_i2c_bus_get_irq() argument
1514 return bus->controller->irq; in aspeed_2500_i2c_bus_get_irq()
1517 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) in aspeed_2500_i2c_bus_pool_base() argument
1519 return bus->pool; in aspeed_2500_i2c_bus_pool_base()
1547 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) in aspeed_2600_i2c_bus_get_irq() argument
1549 return bus->irq; in aspeed_2600_i2c_bus_get_irq()
1645 I2CBus *bus = NULL; in type_init() local
1648 bus = s->busses[busnr].bus; in type_init()
1651 return bus; in type_init()