Lines Matching +full:0 +full:x25f
120 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_old_read()
131 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); in aspeed_i2c_bus_old_read()
167 value = extract64(bus->dma_dram_offset, 0, 32); in aspeed_i2c_bus_new_read()
186 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); in aspeed_i2c_bus_new_read()
241 return 0; in aspeed_i2c_dma_read()
257 for (i = 0; i < pool_tx_count; i++) { in aspeed_i2c_bus_send()
267 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); in aspeed_i2c_bus_send()
271 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); in aspeed_i2c_bus_send()
289 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); in aspeed_i2c_bus_send()
291 trace_aspeed_i2c_bus_send("BYTE", 0, 1, in aspeed_i2c_bus_send()
319 for (i = 0; i < pool_rx_count; i++) { in aspeed_i2c_bus_recv()
326 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); in aspeed_i2c_bus_recv()
327 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); in aspeed_i2c_bus_recv()
331 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_recv()
359 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); in aspeed_i2c_bus_recv()
378 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); in aspeed_i2c_handle_rx_cmd()
379 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); in aspeed_i2c_handle_rx_cmd()
396 return pool_base[0]; in aspeed_i2c_get_addr()
490 extract32(addr, 0, 1))) { in aspeed_i2c_bus_handle_cmd()
502 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); in aspeed_i2c_bus_handle_cmd()
505 if (bus->regs[reg_dma_len] == 0) { in aspeed_i2c_bus_handle_cmd()
506 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
509 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
531 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); in aspeed_i2c_bus_handle_cmd()
553 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); in aspeed_i2c_bus_handle_cmd()
578 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; in aspeed_i2c_bus_new_write()
585 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; in aspeed_i2c_bus_new_write()
586 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); in aspeed_i2c_bus_new_write()
589 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; in aspeed_i2c_bus_new_write()
598 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; in aspeed_i2c_bus_new_write()
606 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); in aspeed_i2c_bus_new_write()
637 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { in aspeed_i2c_bus_new_write()
643 value &= 0xff0ffbfb; in aspeed_i2c_bus_new_write()
657 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_write()
666 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_write()
689 /* Writes clear to 0 */ in aspeed_i2c_bus_new_write()
690 bus->regs[R_I2CM_DMA_LEN_STS] = 0; in aspeed_i2c_bus_new_write()
703 assert(FIELD_EX32(value, I2CS_DMA_LEN, TX_BUF_LEN) == 0); in aspeed_i2c_bus_new_write()
727 bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000; in aspeed_i2c_bus_new_write()
739 bus->regs[R_I2CS_DMA_LEN_STS] = 0; in aspeed_i2c_bus_new_write()
748 * The DRAM offset range is from 0x0_0000_0000 to in aspeed_i2c_bus_new_write()
749 * 0x1_FFFF_FFFF and it is enough to use bits [33:0] in aspeed_i2c_bus_new_write()
751 * Therefore, save the high part physical address bit[1:0] in aspeed_i2c_bus_new_write()
764 extract32(value, 0, 2)); in aspeed_i2c_bus_new_write()
776 extract32(value, 0, 2)); in aspeed_i2c_bus_new_write()
793 extract32(value, 0, 2)); in aspeed_i2c_bus_new_write()
796 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in aspeed_i2c_bus_new_write()
814 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; in aspeed_i2c_bus_old_write()
817 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; in aspeed_i2c_bus_old_write()
820 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; in aspeed_i2c_bus_old_write()
823 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; in aspeed_i2c_bus_old_write()
828 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); in aspeed_i2c_bus_old_write()
848 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; in aspeed_i2c_bus_old_write()
849 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); in aspeed_i2c_bus_old_write()
873 bus->regs[R_I2CD_CMD] &= ~0xFFFF; in aspeed_i2c_bus_old_write()
874 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; in aspeed_i2c_bus_old_write()
885 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_old_write()
886 value & 0x3ffffffc); in aspeed_i2c_bus_old_write()
895 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; in aspeed_i2c_bus_old_write()
902 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in aspeed_i2c_bus_old_write()
932 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in aspeed_i2c_ctrl_read()
936 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in aspeed_i2c_ctrl_read()
957 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx in aspeed_i2c_ctrl_write()
963 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in aspeed_i2c_ctrl_write()
985 uint64_t ret = 0; in aspeed_i2c_share_pool_read()
988 for (i = 0; i < size; i++) { in aspeed_i2c_share_pool_read()
1001 for (i = 0; i < size; i++) { in aspeed_i2c_share_pool_write()
1002 s->share_pool[offset + i] = (value >> (8 * i)) & 0xFF; in aspeed_i2c_share_pool_write()
1020 uint64_t ret = 0; in aspeed_i2c_bus_pool_read()
1023 for (i = 0; i < size; i++) { in aspeed_i2c_bus_pool_read()
1036 for (i = 0; i < size; i++) { in aspeed_i2c_bus_pool_write()
1037 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; in aspeed_i2c_bus_pool_write()
1082 s->intr_status = 0; in aspeed_i2c_reset()
1091 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_instance_init()
1100 * 0x000 ... 0x03F: Global Register
1101 * 0x040 ... 0x07F: Device 1
1102 * 0x080 ... 0x0BF: Device 2
1103 * 0x0C0 ... 0x0FF: Device 3
1104 * 0x100 ... 0x13F: Device 4
1105 * 0x140 ... 0x17F: Device 5
1106 * 0x180 ... 0x1BF: Device 6
1107 * 0x1C0 ... 0x1FF: Device 7
1108 * 0x200 ... 0x20F: Device 1 buffer (AST2500 unused in linux driver)
1109 * 0x210 ... 0x21F: Device 2 buffer
1110 * 0x220 ... 0x22F: Device 3 buffer
1111 * 0x230 ... 0x23F: Device 4 buffer
1112 * 0x240 ... 0x24F: Device 5 buffer
1113 * 0x250 ... 0x25F: Device 6 buffer
1114 * 0x260 ... 0x26F: Device 7 buffer
1115 * 0x270 ... 0x27F: Device 8 buffer
1116 * 0x280 ... 0x28F: Device 9 buffer
1117 * 0x290 ... 0x29F: Device 10 buffer
1118 * 0x2A0 ... 0x2AF: Device 11 buffer
1119 * 0x2B0 ... 0x2BF: Device 12 buffer
1120 * 0x2C0 ... 0x2CF: Device 13 buffer
1121 * 0x2D0 ... 0x2DF: Device 14 buffer
1122 * 0x2E0 ... 0x2FF: Reserved
1123 * 0x300 ... 0x33F: Device 8
1124 * 0x340 ... 0x37F: Device 9
1125 * 0x380 ... 0x3BF: Device 10
1126 * 0x3C0 ... 0x3FF: Device 11
1127 * 0x400 ... 0x43F: Device 12
1128 * 0x440 ... 0x47F: Device 13
1129 * 0x480 ... 0x4BF: Device 14
1130 * 0x800 ... 0xFFF: Buffer Pool (AST2400 unused in linux driver)
1133 * 0x000 ... 0x07F: Global Register
1134 * 0x080 ... 0x0FF: Device 1
1135 * 0x100 ... 0x17F: Device 2
1136 * 0x180 ... 0x1FF: Device 3
1137 * 0x200 ... 0x27F: Device 4
1138 * 0x280 ... 0x2FF: Device 5
1139 * 0x300 ... 0x37F: Device 6
1140 * 0x380 ... 0x3FF: Device 7
1141 * 0x400 ... 0x47F: Device 8
1142 * 0x480 ... 0x4FF: Device 9
1143 * 0x500 ... 0x57F: Device 10
1144 * 0x580 ... 0x5FF: Device 11
1145 * 0x600 ... 0x67F: Device 12
1146 * 0x680 ... 0x6FF: Device 13
1147 * 0x700 ... 0x77F: Device 14
1148 * 0x780 ... 0x7FF: Device 15 (15 and 16 unused in AST1030)
1149 * 0x800 ... 0x87F: Device 16
1150 * 0xC00 ... 0xC1F: Device 1 buffer
1151 * 0xC20 ... 0xC3F: Device 2 buffer
1152 * 0xC40 ... 0xC5F: Device 3 buffer
1153 * 0xC60 ... 0xC7F: Device 4 buffer
1154 * 0xC80 ... 0xC9F: Device 5 buffer
1155 * 0xCA0 ... 0xCBF: Device 6 buffer
1156 * 0xCC0 ... 0xCDF: Device 7 buffer
1157 * 0xCE0 ... 0xCFF: Device 8 buffer
1158 * 0xD00 ... 0xD1F: Device 9 buffer
1159 * 0xD20 ... 0xD3F: Device 10 buffer
1160 * 0xD40 ... 0xD5F: Device 11 buffer
1161 * 0xD60 ... 0xD7F: Device 12 buffer
1162 * 0xD80 ... 0xD9F: Device 13 buffer
1163 * 0xDA0 ... 0xDBF: Device 14 buffer
1164 * 0xDC0 ... 0xDDF: Device 15 buffer (15 and 16 unused in AST1030)
1165 * 0xDE0 ... 0xDFF: Device 16 buffer
1168 * 0x000 ... 0x0FF: Global Register
1169 * 0x100 ... 0x17F: Device 0
1170 * 0x1A0 ... 0x1BF: Device 0 buffer
1171 * 0x200 ... 0x27F: Device 1
1172 * 0x2A0 ... 0x2BF: Device 1 buffer
1173 * 0x300 ... 0x37F: Device 2
1174 * 0x3A0 ... 0x3BF: Device 2 buffer
1175 * 0x400 ... 0x47F: Device 3
1176 * 0x4A0 ... 0x4BF: Device 3 buffer
1177 * 0x500 ... 0x57F: Device 4
1178 * 0x5A0 ... 0x5BF: Device 4 buffer
1179 * 0x600 ... 0x67F: Device 5
1180 * 0x6A0 ... 0x6BF: Device 5 buffer
1181 * 0x700 ... 0x77F: Device 6
1182 * 0x7A0 ... 0x7BF: Device 6 buffer
1183 * 0x800 ... 0x87F: Device 7
1184 * 0x8A0 ... 0x8BF: Device 7 buffer
1185 * 0x900 ... 0x97F: Device 8
1186 * 0x9A0 ... 0x9BF: Device 8 buffer
1187 * 0xA00 ... 0xA7F: Device 9
1188 * 0xAA0 ... 0xABF: Device 9 buffer
1189 * 0xB00 ... 0xB7F: Device 10
1190 * 0xBA0 ... 0xBBF: Device 10 buffer
1191 * 0xC00 ... 0xC7F: Device 11
1192 * 0xCA0 ... 0xCBF: Device 11 buffer
1193 * 0xD00 ... 0xD7F: Device 12
1194 * 0xDA0 ... 0xDBF: Device 12 buffer
1195 * 0xE00 ... 0xE7F: Device 13
1196 * 0xEA0 ... 0xEBF: Device 13 buffer
1197 * 0xF00 ... 0xF7F: Device 14
1198 * 0xFA0 ... 0xFBF: Device 14 buffer
1199 * 0x1000 ... 0x107F: Device 15
1200 * 0x10A0 ... 0x10BF: Device 15 buffer
1216 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_realize()
1243 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_realize()
1298 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_new_slave_event()
1300 deposit64(bus->dma_dram_offset, 0, 32, in aspeed_i2c_bus_new_slave_event()
1319 return 0; in aspeed_i2c_bus_new_slave_event()
1338 /* Bit[0] == 0 indicates "send". */ in aspeed_i2c_bus_slave_event()
1361 return 0; in aspeed_i2c_bus_slave_event()
1416 memset(s->regs, 0, sizeof(s->regs)); in aspeed_i2c_bus_reset()
1438 0xff); in aspeed_i2c_bus_realize()
1450 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
1483 POOL_PAGE_SEL) * 0x100]; in aspeed_2400_i2c_bus_pool_base()
1496 aic->reg_size = 0x40; in aspeed_2400_i2c_class_init()
1500 aic->pool_size = 0x800; in aspeed_2400_i2c_class_init()
1501 aic->pool_base = 0x800; in aspeed_2400_i2c_class_init()
1503 aic->mem_size = 0x1000; in aspeed_2400_i2c_class_init()
1530 aic->reg_size = 0x40; in aspeed_2500_i2c_class_init()
1533 aic->pool_size = 0x10; in aspeed_2500_i2c_class_init()
1534 aic->pool_base = 0x200; in aspeed_2500_i2c_class_init()
1538 aic->mem_size = 0x1000; in aspeed_2500_i2c_class_init()
1560 aic->reg_size = 0x80; in aspeed_2600_i2c_class_init()
1563 aic->pool_size = 0x20; in aspeed_2600_i2c_class_init()
1564 aic->pool_base = 0xC00; in aspeed_2600_i2c_class_init()
1567 aic->mem_size = 0x1000; in aspeed_2600_i2c_class_init()
1584 aic->reg_size = 0x80; in aspeed_1030_i2c_class_init()
1587 aic->pool_size = 0x20; in aspeed_1030_i2c_class_init()
1588 aic->pool_base = 0xC00; in aspeed_1030_i2c_class_init()
1591 aic->mem_size = 0x10000; in aspeed_1030_i2c_class_init()
1608 aic->reg_size = 0x80; in aspeed_2700_i2c_class_init()
1609 aic->reg_gap_size = 0x80; in aspeed_2700_i2c_class_init()
1612 aic->pool_size = 0x20; in aspeed_2700_i2c_class_init()
1613 aic->pool_gap_size = 0xe0; in aspeed_2700_i2c_class_init()
1614 aic->pool_base = 0x1a0; in aspeed_2700_i2c_class_init()
1617 aic->mem_size = 0x2000; in aspeed_2700_i2c_class_init()
1647 if (busnr >= 0 && busnr < aic->num_busses) { in type_init()