Lines Matching +full:attr +full:- +full:cnt +full:- +full:name
30 #include "hw/dma/xlnx-zdma.h"
32 #include "hw/qdev-properties.h"
156 FIELD(ZDMA_CH_RATE_CTRL, CNT, 0, 12)
171 FIELD(ZDMA_CH_RATE_CNTL, CNT, 0, 12)
173 FIELD(ZDMA_CH_IRQ_SRC_ACCT, CNT, 0, 8)
175 FIELD(ZDMA_CH_IRQ_DST_ACCT, CNT, 0, 8)
213 pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR]; in zdma_ch_imr_update_irq()
215 qemu_set_irq(s->irq_zdma_ch_imr, pending); in zdma_ch_imr_update_irq()
220 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_isr_postw()
226 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_ien_prew()
229 s->regs[R_ZDMA_CH_IMR] &= ~val; in zdma_ch_ien_prew()
236 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_ids_prew()
239 s->regs[R_ZDMA_CH_IMR] |= val; in zdma_ch_ids_prew()
246 s->state = state; in zdma_set_state()
247 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state); in zdma_set_state()
250 if (s->error) { in zdma_set_state()
251 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3); in zdma_set_state()
257 unsigned int cnt; in zdma_src_done() local
258 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT); in zdma_src_done()
259 cnt++; in zdma_src_done()
260 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt); in zdma_src_done()
261 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true); in zdma_src_done()
264 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) { in zdma_src_done()
265 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true); in zdma_src_done()
272 unsigned int cnt; in zdma_dst_done() local
273 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT); in zdma_dst_done()
274 cnt++; in zdma_dst_done()
275 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt); in zdma_dst_done()
276 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true); in zdma_dst_done()
279 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) { in zdma_dst_done()
280 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true); in zdma_dst_done()
289 addr = s->regs[basereg + 1]; in zdma_get_regaddr64()
291 addr |= s->regs[basereg]; in zdma_get_regaddr64()
298 s->regs[basereg] = addr; in zdma_put_regaddr64()
299 s->regs[basereg + 1] = addr >> 32; in zdma_put_regaddr64()
305 descr->addr = zdma_get_regaddr64(s, reg); in zdma_load_descriptor_reg()
306 descr->size = s->regs[reg + 2]; in zdma_load_descriptor_reg()
307 descr->attr = s->regs[reg + 3]; in zdma_load_descriptor_reg()
319 s->error = true; in zdma_load_descriptor()
323 descr->addr = address_space_ldq_le(&s->dma_as, addr, s->attr, NULL); in zdma_load_descriptor()
324 descr->size = address_space_ldl_le(&s->dma_as, addr + 8, s->attr, NULL); in zdma_load_descriptor()
325 descr->attr = address_space_ldl_le(&s->dma_as, addr + 12, s->attr, NULL); in zdma_load_descriptor()
332 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_load_src_descriptor()
335 zdma_load_descriptor_reg(s, R_ZDMA_CH_SRC_DSCR_WORD0, &s->dsc_src); in zdma_load_src_descriptor()
341 if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) { in zdma_load_src_descriptor()
342 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true); in zdma_load_src_descriptor()
353 next = addr + sizeof(s->dsc_dst); in zdma_update_descr_addr()
356 addr += sizeof(s->dsc_dst); in zdma_update_descr_addr()
357 next = address_space_ldq_le(&s->dma_as, addr, s->attr, NULL); in zdma_update_descr_addr()
366 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_load_dst_descriptor()
370 zdma_load_descriptor_reg(s, R_ZDMA_CH_DST_DSCR_WORD0, &s->dsc_dst); in zdma_load_dst_descriptor()
376 if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) { in zdma_load_dst_descriptor()
377 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true); in zdma_load_dst_descriptor()
381 dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, TYPE); in zdma_load_dst_descriptor()
389 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_write_dst()
390 unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE); in zdma_write_dst()
391 unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR, in zdma_write_dst()
400 dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2, in zdma_write_dst()
404 dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2, in zdma_write_dst()
414 dst_intr = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, in zdma_write_dst()
419 if (dlen > (s->cfg.bus_width / 8)) { in zdma_write_dst()
420 dlen = s->cfg.bus_width / 8; in zdma_write_dst()
424 address_space_write(&s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen); in zdma_write_dst()
426 s->dsc_dst.addr += dlen; in zdma_write_dst()
428 dst_size -= dlen; in zdma_write_dst()
430 len -= dlen; in zdma_write_dst()
437 s->dsc_dst.words[2] = FIELD_DP32(s->dsc_dst.words[2], in zdma_write_dst()
450 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_process_descr()
451 unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE); in zdma_process_descr()
452 unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR, in zdma_process_descr()
455 src_addr = s->dsc_src.addr; in zdma_process_descr()
456 src_size = FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, SIZE); in zdma_process_descr()
457 src_cmd = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, CMD); in zdma_process_descr()
458 src_type = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, TYPE); in zdma_process_descr()
459 src_intr = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, INTR); in zdma_process_descr()
461 /* FIXED burst types and non-rw modes are only supported in in zdma_process_descr()
467 "zDMA: rw-mode=%d but not simple DMA mode.\n", in zdma_process_descr()
480 /* In Simple DMA Write-Only, we need to push DST size bytes in zdma_process_descr()
482 src_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2, in zdma_process_descr()
484 memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width / 8); in zdma_process_descr()
488 len = src_size > ARRAY_SIZE(s->buf) ? ARRAY_SIZE(s->buf) : src_size; in zdma_process_descr()
490 if (len > (s->cfg.bus_width / 8)) { in zdma_process_descr()
491 len = s->cfg.bus_width / 8; in zdma_process_descr()
496 if (len > s->cfg.bus_width / 8) { in zdma_process_descr()
497 len = s->cfg.bus_width / 8; in zdma_process_descr()
500 address_space_read(&s->dma_as, src_addr, s->attr, s->buf, len); in zdma_process_descr()
507 zdma_write_dst(s, s->buf, len); in zdma_process_descr()
510 s->regs[R_ZDMA_CH_TOTAL_BYTE] += len; in zdma_process_descr()
511 src_size -= len; in zdma_process_descr()
514 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true); in zdma_process_descr()
521 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0); in zdma_process_descr()
527 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1); in zdma_process_descr()
528 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, false); in zdma_process_descr()
538 while (s->state == ENABLED && !s->error) { in zdma_run()
541 if (s->error) { in zdma_run()
564 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_ctrlx_postw()
566 if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL2, EN)) { in zdma_ch_ctrlx_postw()
567 s->error = false; in zdma_ch_ctrlx_postw()
569 if (s->state == PAUSED && in zdma_ch_ctrlx_postw()
570 ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) { in zdma_ch_ctrlx_postw()
571 if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT_ADDR) == 1) { in zdma_ch_ctrlx_postw()
574 bool src_type = FIELD_EX32(s->dsc_src.words[3], in zdma_ch_ctrlx_postw()
579 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL0, CONT, false); in zdma_ch_ctrlx_postw()
581 } else if (s->state == DISABLED) { in zdma_ch_ctrlx_postw()
587 if (s->state == PAUSED && in zdma_ch_ctrlx_postw()
588 ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) { in zdma_ch_ctrlx_postw()
597 { .name = "ZDMA_ERR_CTRL", .addr = A_ZDMA_ERR_CTRL,
599 },{ .name = "ZDMA_CH_ISR", .addr = A_ZDMA_CH_ISR,
603 },{ .name = "ZDMA_CH_IMR", .addr = A_ZDMA_CH_IMR,
607 },{ .name = "ZDMA_CH_IEN", .addr = A_ZDMA_CH_IEN,
610 },{ .name = "ZDMA_CH_IDS", .addr = A_ZDMA_CH_IDS,
613 },{ .name = "ZDMA_CH_CTRL0", .addr = A_ZDMA_CH_CTRL0,
617 },{ .name = "ZDMA_CH_CTRL1", .addr = A_ZDMA_CH_CTRL1,
620 },{ .name = "ZDMA_CH_FCI", .addr = A_ZDMA_CH_FCI,
622 },{ .name = "ZDMA_CH_STATUS", .addr = A_ZDMA_CH_STATUS,
625 },{ .name = "ZDMA_CH_DATA_ATTR", .addr = A_ZDMA_CH_DATA_ATTR,
628 },{ .name = "ZDMA_CH_DSCR_ATTR", .addr = A_ZDMA_CH_DSCR_ATTR,
630 },{ .name = "ZDMA_CH_SRC_DSCR_WORD0", .addr = A_ZDMA_CH_SRC_DSCR_WORD0,
631 },{ .name = "ZDMA_CH_SRC_DSCR_WORD1", .addr = A_ZDMA_CH_SRC_DSCR_WORD1,
633 },{ .name = "ZDMA_CH_SRC_DSCR_WORD2", .addr = A_ZDMA_CH_SRC_DSCR_WORD2,
635 },{ .name = "ZDMA_CH_SRC_DSCR_WORD3", .addr = A_ZDMA_CH_SRC_DSCR_WORD3,
637 },{ .name = "ZDMA_CH_DST_DSCR_WORD0", .addr = A_ZDMA_CH_DST_DSCR_WORD0,
638 },{ .name = "ZDMA_CH_DST_DSCR_WORD1", .addr = A_ZDMA_CH_DST_DSCR_WORD1,
640 },{ .name = "ZDMA_CH_DST_DSCR_WORD2", .addr = A_ZDMA_CH_DST_DSCR_WORD2,
642 },{ .name = "ZDMA_CH_DST_DSCR_WORD3", .addr = A_ZDMA_CH_DST_DSCR_WORD3,
644 },{ .name = "ZDMA_CH_WR_ONLY_WORD0", .addr = A_ZDMA_CH_WR_ONLY_WORD0,
645 },{ .name = "ZDMA_CH_WR_ONLY_WORD1", .addr = A_ZDMA_CH_WR_ONLY_WORD1,
646 },{ .name = "ZDMA_CH_WR_ONLY_WORD2", .addr = A_ZDMA_CH_WR_ONLY_WORD2,
647 },{ .name = "ZDMA_CH_WR_ONLY_WORD3", .addr = A_ZDMA_CH_WR_ONLY_WORD3,
648 },{ .name = "ZDMA_CH_SRC_START_LSB", .addr = A_ZDMA_CH_SRC_START_LSB,
649 },{ .name = "ZDMA_CH_SRC_START_MSB", .addr = A_ZDMA_CH_SRC_START_MSB,
651 },{ .name = "ZDMA_CH_DST_START_LSB", .addr = A_ZDMA_CH_DST_START_LSB,
652 },{ .name = "ZDMA_CH_DST_START_MSB", .addr = A_ZDMA_CH_DST_START_MSB,
654 },{ .name = "ZDMA_CH_SRC_CUR_PYLD_LSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_LSB,
656 },{ .name = "ZDMA_CH_SRC_CUR_PYLD_MSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_MSB,
659 },{ .name = "ZDMA_CH_DST_CUR_PYLD_LSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_LSB,
661 },{ .name = "ZDMA_CH_DST_CUR_PYLD_MSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_MSB,
664 },{ .name = "ZDMA_CH_SRC_CUR_DSCR_LSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_LSB,
666 },{ .name = "ZDMA_CH_SRC_CUR_DSCR_MSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_MSB,
669 },{ .name = "ZDMA_CH_DST_CUR_DSCR_LSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_LSB,
671 },{ .name = "ZDMA_CH_DST_CUR_DSCR_MSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_MSB,
674 },{ .name = "ZDMA_CH_TOTAL_BYTE", .addr = A_ZDMA_CH_TOTAL_BYTE,
676 },{ .name = "ZDMA_CH_RATE_CNTL", .addr = A_ZDMA_CH_RATE_CNTL,
678 },{ .name = "ZDMA_CH_IRQ_SRC_ACCT", .addr = A_ZDMA_CH_IRQ_SRC_ACCT,
682 },{ .name = "ZDMA_CH_IRQ_DST_ACCT", .addr = A_ZDMA_CH_IRQ_DST_ACCT,
686 },{ .name = "ZDMA_CH_DBG0", .addr = A_ZDMA_CH_DBG0,
695 },{ .name = "ZDMA_CH_DBG1", .addr = A_ZDMA_CH_DBG1,
698 },{ .name = "ZDMA_CH_CTRL2", .addr = A_ZDMA_CH_CTRL2,
709 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in zdma_reset()
710 register_reset(&s->regs_info[i]); in zdma_reset()
719 RegisterInfo *r = &s->regs_info[addr / 4]; in zdma_read()
721 if (!r->data) { in zdma_read()
727 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); in zdma_read()
738 RegisterInfo *r = &s->regs_info[addr / 4]; in zdma_write()
740 if (!r->data) { in zdma_write()
746 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); in zdma_write()
768 if (!s->dma_mr) { in zdma_realize()
772 address_space_init(&s->dma_as, s->dma_mr, "zdma-dma"); in zdma_realize()
775 RegisterInfo *r = &s->regs_info[zdma_regs_info[i].addr / 4]; in zdma_realize()
778 .data = (uint8_t *)&s->regs[ in zdma_realize()
786 s->attr = MEMTXATTRS_UNSPECIFIED; in zdma_realize()
794 memory_region_init_io(&s->iomem, obj, &zdma_ops, s, in zdma_init()
796 sysbus_init_mmio(sbd, &s->iomem); in zdma_init()
797 sysbus_init_irq(sbd, &s->irq_zdma_ch_imr); in zdma_init()
801 .name = TYPE_XLNX_ZDMA,
814 DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
825 dc->realize = zdma_realize; in zdma_class_init()
827 dc->vmsd = &vmstate_zdma; in zdma_class_init()
831 .name = TYPE_XLNX_ZDMA,