Lines Matching full:pl330
2 * ARM PrimeCell PL330 DMA Controller
96 /* DMA channel states as they are described in PL330 Technical Reference Manual
277 #define TYPE_PL330 "pl330"
278 OBJECT_DECLARE_SIMPLE_TYPE(PL330State, PL330)
281 .name = "pl330",
469 * nature of the instruction: is it load or store. PL330 has different queues
608 * For information about instructions see PL330 Technical Reference Manual.
1333 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " in pl330_debug_exec()
1368 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " in pl330_iomem_write()
1380 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx in pl330_iomem_write()
1404 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " in pl330_iomem_read_imp()
1420 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " in pl330_iomem_read_imp()
1429 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " in pl330_iomem_read_imp()
1443 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n"); in pl330_iomem_read_imp()
1451 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " in pl330_iomem_read_imp()
1490 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " in pl330_iomem_read_imp()
1532 PL330State *s = PL330(d); in pl330_reset()
1557 PL330State *s = PL330(dev); in pl330_realize()