Lines Matching refs:dpcd_info
47 uint8_t dpcd_info[DPCD_READABLE_AREA]; member
58 ret = e->dpcd_info[offset]; in dpcd_read()
76 e->dpcd_info[offset] = value; in dpcd_write()
100 memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info)); in dpcd_reset()
102 s->dpcd_info[DPCD_REVISION] = DPCD_REV_1_0; in dpcd_reset()
103 s->dpcd_info[DPCD_MAX_LINK_RATE] = DPCD_5_4GBPS; in dpcd_reset()
104 s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES; in dpcd_reset()
105 s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_0] = DPCD_EDID_PRESENT; in dpcd_reset()
107 s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF; in dpcd_reset()
109 s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE in dpcd_reset()
115 s->dpcd_info[DPCD_LANE2_3_STATUS] = DPCD_LANE2_CR_DONE in dpcd_reset()
122 s->dpcd_info[DPCD_LANE_ALIGN_STATUS_UPDATED] = DPCD_INTERLANE_ALIGN_DONE; in dpcd_reset()
123 s->dpcd_info[DPCD_SINK_STATUS] = DPCD_RECEIVE_PORT_0_STATUS; in dpcd_reset()
139 VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
152 static const TypeInfo dpcd_info = { variable
162 type_register_static(&dpcd_info); in dpcd_register_types()