Lines Matching +full:standard +full:- +full:mode
43 #include "hw/qdev-properties.h"
53 * - destination write mask support not complete (bits 5..7)
54 * - optimize linear mappings
55 * - optimize bitblt functions
147 // memory-mapped IO
189 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
218 + ((int64_t)s->cirrus_blt_height - 1) * pitch in blit_region_is_unsafe()
219 - s->cirrus_blt_width; in blit_region_is_unsafe()
220 if (min < -1 || addr >= s->vga.vram_size) { in blit_region_is_unsafe()
225 + ((int64_t)s->cirrus_blt_height-1) * pitch in blit_region_is_unsafe()
226 + s->cirrus_blt_width; in blit_region_is_unsafe()
227 if (max > s->vga.vram_size) { in blit_region_is_unsafe()
237 assert(s->cirrus_blt_width > 0); in blit_is_unsafe()
238 assert(s->cirrus_blt_height > 0); in blit_is_unsafe()
240 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) { in blit_is_unsafe()
244 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch, in blit_is_unsafe()
245 s->cirrus_blt_dstaddr)) { in blit_is_unsafe()
251 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch, in blit_is_unsafe()
252 s->cirrus_blt_srcaddr)) { in blit_is_unsafe()
274 if (s->cirrus_srccounter) { in cirrus_src()
276 return s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1)]; in cirrus_src()
279 return s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask]; in cirrus_src()
287 if (s->cirrus_srccounter) { in cirrus_src16()
289 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~1]; in cirrus_src16()
292 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~1]; in cirrus_src16()
301 if (s->cirrus_srccounter) { in cirrus_src32()
303 src = (void *)&s->cirrus_bltbuf[srcaddr & (CIRRUS_BLTBUFSIZE - 1) & ~3]; in cirrus_src32()
306 src = (void *)&s->vga.vram_ptr[srcaddr & s->cirrus_addr_mask & ~3]; in cirrus_src32()
587 switch (s->cirrus_blt_pixelwidth) { in cirrus_bitblt_fgcol()
589 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; in cirrus_bitblt_fgcol()
592 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); in cirrus_bitblt_fgcol()
593 s->cirrus_blt_fgcol = le16_to_cpu(color); in cirrus_bitblt_fgcol()
596 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | in cirrus_bitblt_fgcol()
597 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); in cirrus_bitblt_fgcol()
601 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | in cirrus_bitblt_fgcol()
602 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); in cirrus_bitblt_fgcol()
603 s->cirrus_blt_fgcol = le32_to_cpu(color); in cirrus_bitblt_fgcol()
611 switch (s->cirrus_blt_pixelwidth) { in cirrus_bitblt_bgcol()
613 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; in cirrus_bitblt_bgcol()
616 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); in cirrus_bitblt_bgcol()
617 s->cirrus_blt_bgcol = le16_to_cpu(color); in cirrus_bitblt_bgcol()
620 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | in cirrus_bitblt_bgcol()
621 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); in cirrus_bitblt_bgcol()
625 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | in cirrus_bitblt_bgcol()
626 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); in cirrus_bitblt_bgcol()
627 s->cirrus_blt_bgcol = le32_to_cpu(color); in cirrus_bitblt_bgcol()
641 off_begin -= bytesperline - 1; in cirrus_invalidate_region()
645 off_cur = off_begin & s->cirrus_addr_mask; in cirrus_invalidate_region()
646 off_cur_end = ((off_cur + bytesperline - 1) & s->cirrus_addr_mask) + 1; in cirrus_invalidate_region()
648 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); in cirrus_invalidate_region()
651 memory_region_set_dirty(&s->vga.vram, off_cur, in cirrus_invalidate_region()
652 s->cirrus_addr_mask + 1 - off_cur); in cirrus_invalidate_region()
653 memory_region_set_dirty(&s->vga.vram, 0, off_cur_end); in cirrus_invalidate_region()
662 bool videosrc = !s->cirrus_srccounter; in cirrus_bitblt_common_patterncopy()
665 switch (s->vga.get_bpp(&s->vga)) { in cirrus_bitblt_common_patterncopy()
679 s->cirrus_blt_srcaddr &= ~(patternsize - 1); in cirrus_bitblt_common_patterncopy()
680 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) { in cirrus_bitblt_common_patterncopy()
689 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr, in cirrus_bitblt_common_patterncopy()
690 videosrc ? s->cirrus_blt_srcaddr : 0, in cirrus_bitblt_common_patterncopy()
691 s->cirrus_blt_dstpitch, 0, in cirrus_bitblt_common_patterncopy()
692 s->cirrus_blt_width, s->cirrus_blt_height); in cirrus_bitblt_common_patterncopy()
693 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, in cirrus_bitblt_common_patterncopy()
694 s->cirrus_blt_dstpitch, s->cirrus_blt_width, in cirrus_bitblt_common_patterncopy()
695 s->cirrus_blt_height); in cirrus_bitblt_common_patterncopy()
708 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_solidfill()
709 rop_func(s, s->cirrus_blt_dstaddr, in cirrus_bitblt_solidfill()
710 s->cirrus_blt_dstpitch, in cirrus_bitblt_solidfill()
711 s->cirrus_blt_width, s->cirrus_blt_height); in cirrus_bitblt_solidfill()
712 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, in cirrus_bitblt_solidfill()
713 s->cirrus_blt_dstpitch, s->cirrus_blt_width, in cirrus_bitblt_solidfill()
714 s->cirrus_blt_height); in cirrus_bitblt_solidfill()
721 * bitblt (video-to-video)
738 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src || in cirrus_do_copy()
739 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { in cirrus_do_copy()
743 depth = s->vga.get_bpp(&s->vga) / 8; in cirrus_do_copy()
747 s->vga.get_resolution(&s->vga, &width, &height); in cirrus_do_copy()
750 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; in cirrus_do_copy()
751 sy = (src / ABS(s->cirrus_blt_srcpitch)); in cirrus_do_copy()
752 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; in cirrus_do_copy()
753 dy = (dst / ABS(s->cirrus_blt_dstpitch)); in cirrus_do_copy()
761 if (s->cirrus_blt_dstpitch < 0) { in cirrus_do_copy()
762 sx -= (s->cirrus_blt_width / depth) - 1; in cirrus_do_copy()
763 dx -= (s->cirrus_blt_width / depth) - 1; in cirrus_do_copy()
764 sy -= s->cirrus_blt_height - 1; in cirrus_do_copy()
765 dy -= s->cirrus_blt_height - 1; in cirrus_do_copy()
776 (*s->cirrus_rop) (s, s->cirrus_blt_dstaddr, in cirrus_do_copy()
777 s->cirrus_blt_srcaddr, in cirrus_do_copy()
778 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, in cirrus_do_copy()
779 s->cirrus_blt_width, s->cirrus_blt_height); in cirrus_do_copy()
782 dpy_gfx_update(s->vga.con, dx, dy, in cirrus_do_copy()
783 s->cirrus_blt_width / depth, in cirrus_do_copy()
784 s->cirrus_blt_height); in cirrus_do_copy()
790 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, in cirrus_do_copy()
791 s->cirrus_blt_dstpitch, s->cirrus_blt_width, in cirrus_do_copy()
792 s->cirrus_blt_height); in cirrus_do_copy()
802 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.params.start_addr, in cirrus_bitblt_videotovideo_copy()
803 s->cirrus_blt_srcaddr - s->vga.params.start_addr, in cirrus_bitblt_videotovideo_copy()
804 s->cirrus_blt_width, s->cirrus_blt_height); in cirrus_bitblt_videotovideo_copy()
809 * bitblt (cpu-to-video)
818 if (s->cirrus_srccounter > 0) { in cirrus_bitblt_cputovideo_next()
819 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { in cirrus_bitblt_cputovideo_next()
822 s->cirrus_srccounter = 0; in cirrus_bitblt_cputovideo_next()
827 (*s->cirrus_rop)(s, s->cirrus_blt_dstaddr, in cirrus_bitblt_cputovideo_next()
828 0, 0, 0, s->cirrus_blt_width, 1); in cirrus_bitblt_cputovideo_next()
829 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, in cirrus_bitblt_cputovideo_next()
830 s->cirrus_blt_width, 1); in cirrus_bitblt_cputovideo_next()
831 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; in cirrus_bitblt_cputovideo_next()
832 s->cirrus_srccounter -= s->cirrus_blt_srcpitch; in cirrus_bitblt_cputovideo_next()
833 if (s->cirrus_srccounter <= 0) in cirrus_bitblt_cputovideo_next()
838 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; in cirrus_bitblt_cputovideo_next()
839 copy_count = MIN(s->cirrus_srcptr_end - end_ptr, CIRRUS_BLTBUFSIZE); in cirrus_bitblt_cputovideo_next()
840 memmove(s->cirrus_bltbuf, end_ptr, copy_count); in cirrus_bitblt_cputovideo_next()
841 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; in cirrus_bitblt_cputovideo_next()
842 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; in cirrus_bitblt_cputovideo_next()
843 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end); in cirrus_bitblt_cputovideo_next()
858 s->vga.gr[0x31] &= in cirrus_bitblt_reset()
860 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] in cirrus_bitblt_reset()
861 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
862 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
863 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; in cirrus_bitblt_reset()
864 s->cirrus_srccounter = 0; in cirrus_bitblt_reset()
878 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; in cirrus_bitblt_cputovideo()
879 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; in cirrus_bitblt_cputovideo()
880 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; in cirrus_bitblt_cputovideo()
882 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { in cirrus_bitblt_cputovideo()
883 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { in cirrus_bitblt_cputovideo()
884 s->cirrus_blt_srcpitch = 8; in cirrus_bitblt_cputovideo()
887 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; in cirrus_bitblt_cputovideo()
889 s->cirrus_srccounter = s->cirrus_blt_srcpitch; in cirrus_bitblt_cputovideo()
891 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { in cirrus_bitblt_cputovideo()
892 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; in cirrus_bitblt_cputovideo()
893 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) in cirrus_bitblt_cputovideo()
894 s->cirrus_blt_srcpitch = ((w + 31) >> 5); in cirrus_bitblt_cputovideo()
896 s->cirrus_blt_srcpitch = ((w + 7) >> 3); in cirrus_bitblt_cputovideo()
899 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; in cirrus_bitblt_cputovideo()
901 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; in cirrus_bitblt_cputovideo()
905 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE); in cirrus_bitblt_cputovideo()
907 s->cirrus_srcptr = s->cirrus_bltbuf; in cirrus_bitblt_cputovideo()
908 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; in cirrus_bitblt_cputovideo()
925 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { in cirrus_bitblt_videotovideo()
939 if (!s->enable_blitter) { in cirrus_bitblt_start()
943 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY; in cirrus_bitblt_start()
945 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; in cirrus_bitblt_start()
946 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; in cirrus_bitblt_start()
947 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); in cirrus_bitblt_start()
948 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); in cirrus_bitblt_start()
949 s->cirrus_blt_dstaddr = in cirrus_bitblt_start()
950 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); in cirrus_bitblt_start()
951 s->cirrus_blt_srcaddr = in cirrus_bitblt_start()
952 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); in cirrus_bitblt_start()
953 s->cirrus_blt_mode = s->vga.gr[0x30]; in cirrus_bitblt_start()
954 s->cirrus_blt_modeext = s->vga.gr[0x33]; in cirrus_bitblt_start()
955 blt_rop = s->vga.gr[0x32]; in cirrus_bitblt_start()
957 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask; in cirrus_bitblt_start()
958 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask; in cirrus_bitblt_start()
961 s->cirrus_blt_mode, in cirrus_bitblt_start()
962 s->cirrus_blt_modeext, in cirrus_bitblt_start()
963 s->cirrus_blt_width, in cirrus_bitblt_start()
964 s->cirrus_blt_height, in cirrus_bitblt_start()
965 s->cirrus_blt_dstpitch, in cirrus_bitblt_start()
966 s->cirrus_blt_srcpitch, in cirrus_bitblt_start()
967 s->cirrus_blt_dstaddr, in cirrus_bitblt_start()
968 s->cirrus_blt_srcaddr, in cirrus_bitblt_start()
969 s->vga.gr[0x2f]); in cirrus_bitblt_start()
971 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { in cirrus_bitblt_start()
973 s->cirrus_blt_pixelwidth = 1; in cirrus_bitblt_start()
976 s->cirrus_blt_pixelwidth = 2; in cirrus_bitblt_start()
979 s->cirrus_blt_pixelwidth = 3; in cirrus_bitblt_start()
982 s->cirrus_blt_pixelwidth = 4; in cirrus_bitblt_start()
986 "cirrus: bitblt - pixel width is unknown\n"); in cirrus_bitblt_start()
989 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; in cirrus_bitblt_start()
991 if ((s-> in cirrus_bitblt_start()
996 "cirrus: bitblt - memory-to-memory copy requested\n"); in cirrus_bitblt_start()
1000 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) && in cirrus_bitblt_start()
1001 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | in cirrus_bitblt_start()
1009 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND | in cirrus_bitblt_start()
1013 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { in cirrus_bitblt_start()
1014 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) in cirrus_bitblt_start()
1018 … s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1022 … s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1024 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { in cirrus_bitblt_start()
1025 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { in cirrus_bitblt_start()
1026 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { in cirrus_bitblt_start()
1027 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) in cirrus_bitblt_start()
1031 …s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth … in cirrus_bitblt_start()
1035 … s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1038 … s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1041 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { in cirrus_bitblt_start()
1042 if (s->cirrus_blt_pixelwidth > 2) { in cirrus_bitblt_start()
1048 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { in cirrus_bitblt_start()
1049 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; in cirrus_bitblt_start()
1050 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; in cirrus_bitblt_start()
1051 … s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1053 … s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; in cirrus_bitblt_start()
1056 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { in cirrus_bitblt_start()
1057 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; in cirrus_bitblt_start()
1058 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; in cirrus_bitblt_start()
1059 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; in cirrus_bitblt_start()
1061 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; in cirrus_bitblt_start()
1066 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) { in cirrus_bitblt_start()
1069 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { in cirrus_bitblt_start()
1086 old_value = s->vga.gr[0x31]; in cirrus_write_bitblt()
1087 s->vga.gr[0x31] = reg_value; in cirrus_write_bitblt()
1111 line_offset = s->vga.cr[0x13] in cirrus_get_params()
1112 | ((s->vga.cr[0x1b] & 0x10) << 4); in cirrus_get_params()
1114 params->line_offset = line_offset; in cirrus_get_params()
1116 params->start_addr = (s->vga.cr[0x0c] << 8) in cirrus_get_params()
1117 | s->vga.cr[0x0d] in cirrus_get_params()
1118 | ((s->vga.cr[0x1b] & 0x01) << 16) in cirrus_get_params()
1119 | ((s->vga.cr[0x1b] & 0x0c) << 15) in cirrus_get_params()
1120 | ((s->vga.cr[0x1d] & 0x80) << 12); in cirrus_get_params()
1122 params->line_compare = s->vga.cr[0x18] | in cirrus_get_params()
1123 ((s->vga.cr[0x07] & 0x10) << 4) | in cirrus_get_params()
1124 ((s->vga.cr[0x09] & 0x40) << 3); in cirrus_get_params()
1126 params->hpel = s->vga.ar[VGA_ATC_PEL]; in cirrus_get_params()
1127 params->hpel_split = s->vga.ar[VGA_ATC_MODE] & 0x20; in cirrus_get_params()
1134 switch (s->cirrus_hidden_dac_data & 0xf) { in cirrus_get_bpp16_depth()
1144 (s->cirrus_hidden_dac_data & 0xf)); in cirrus_get_bpp16_depth()
1156 if ((s->vga.sr[0x07] & 0x01) != 0) { in cirrus_get_bpp()
1158 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { in cirrus_get_bpp()
1176 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); in cirrus_get_bpp()
1193 width = (s->cr[0x01] + 1) * 8; in cirrus_get_resolution()
1194 height = s->cr[0x12] | in cirrus_get_resolution()
1195 ((s->cr[0x07] & 0x02) << 7) | in cirrus_get_resolution()
1196 ((s->cr[0x07] & 0x40) << 3); in cirrus_get_resolution()
1199 if (s->cr[0x1a] & 0x01) in cirrus_get_resolution()
1216 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ in cirrus_update_bank_ptr()
1217 offset = s->vga.gr[0x09 + bank_index]; in cirrus_update_bank_ptr()
1219 offset = s->vga.gr[0x09]; in cirrus_update_bank_ptr()
1221 if ((s->vga.gr[0x0b] & 0x20) != 0) in cirrus_update_bank_ptr()
1226 if (s->real_vram_size <= offset) in cirrus_update_bank_ptr()
1229 limit = s->real_vram_size - offset; in cirrus_update_bank_ptr()
1231 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { in cirrus_update_bank_ptr()
1234 limit -= 0x8000; in cirrus_update_bank_ptr()
1241 s->cirrus_bank_base[bank_index] = offset; in cirrus_update_bank_ptr()
1242 s->cirrus_bank_limit[bank_index] = limit; in cirrus_update_bank_ptr()
1244 s->cirrus_bank_base[bank_index] = 0; in cirrus_update_bank_ptr()
1245 s->cirrus_bank_limit[bank_index] = 0; in cirrus_update_bank_ptr()
1251 * I/O access between 0x3c4-0x3c5
1257 switch (s->vga.sr_index) { in cirrus_vga_read_sr()
1258 case 0x00: // Standard VGA in cirrus_vga_read_sr()
1259 case 0x01: // Standard VGA in cirrus_vga_read_sr()
1260 case 0x02: // Standard VGA in cirrus_vga_read_sr()
1261 case 0x03: // Standard VGA in cirrus_vga_read_sr()
1262 case 0x04: // Standard VGA in cirrus_vga_read_sr()
1263 return s->vga.sr[s->vga.sr_index]; in cirrus_vga_read_sr()
1265 return s->vga.sr[s->vga.sr_index]; in cirrus_vga_read_sr()
1274 return s->vga.sr[0x10]; in cirrus_vga_read_sr()
1283 return s->vga.sr[0x11]; in cirrus_vga_read_sr()
1285 case 0x07: // Extended Sequencer Mode in cirrus_vga_read_sr()
1309 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index); in cirrus_vga_read_sr()
1311 return s->vga.sr[s->vga.sr_index]; in cirrus_vga_read_sr()
1314 "cirrus: inport sr_index 0x%02x\n", s->vga.sr_index); in cirrus_vga_read_sr()
1321 switch (s->vga.sr_index) { in cirrus_vga_write_sr()
1322 case 0x00: // Standard VGA in cirrus_vga_write_sr()
1323 case 0x01: // Standard VGA in cirrus_vga_write_sr()
1324 case 0x02: // Standard VGA in cirrus_vga_write_sr()
1325 case 0x03: // Standard VGA in cirrus_vga_write_sr()
1326 case 0x04: // Standard VGA in cirrus_vga_write_sr()
1327 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; in cirrus_vga_write_sr()
1328 if (s->vga.sr_index == 1) in cirrus_vga_write_sr()
1329 s->vga.update_retrace_info(&s->vga); in cirrus_vga_write_sr()
1334 s->vga.sr[s->vga.sr_index] = 0x12; in cirrus_vga_write_sr()
1336 s->vga.sr[s->vga.sr_index] = 0x0f; in cirrus_vga_write_sr()
1347 s->vga.sr[0x10] = val; in cirrus_vga_write_sr()
1348 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); in cirrus_vga_write_sr()
1358 s->vga.sr[0x11] = val; in cirrus_vga_write_sr()
1359 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); in cirrus_vga_write_sr()
1361 case 0x07: // Extended Sequencer Mode in cirrus_vga_write_sr()
1384 s->vga.sr[s->vga.sr_index] = val; in cirrus_vga_write_sr()
1387 s->vga.sr_index, val); in cirrus_vga_write_sr()
1391 s->vga.sr[0x12] = val; in cirrus_vga_write_sr()
1392 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW); in cirrus_vga_write_sr()
1395 val, s->vga.force_shadow); in cirrus_vga_write_sr()
1399 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) in cirrus_vga_write_sr()
1406 s->vga.sr_index, val); in cirrus_vga_write_sr()
1419 if (++s->cirrus_hidden_dac_lockindex == 5) { in cirrus_read_hidden_dac()
1420 s->cirrus_hidden_dac_lockindex = 0; in cirrus_read_hidden_dac()
1421 return s->cirrus_hidden_dac_data; in cirrus_read_hidden_dac()
1428 if (s->cirrus_hidden_dac_lockindex == 4) { in cirrus_write_hidden_dac()
1429 s->cirrus_hidden_dac_data = reg_value; in cirrus_write_hidden_dac()
1434 s->cirrus_hidden_dac_lockindex = 0; in cirrus_write_hidden_dac()
1447 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { in cirrus_vga_read_palette()
1448 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + in cirrus_vga_read_palette()
1449 s->vga.dac_sub_index]; in cirrus_vga_read_palette()
1451 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index]; in cirrus_vga_read_palette()
1453 if (++s->vga.dac_sub_index == 3) { in cirrus_vga_read_palette()
1454 s->vga.dac_sub_index = 0; in cirrus_vga_read_palette()
1455 s->vga.dac_read_index++; in cirrus_vga_read_palette()
1462 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; in cirrus_vga_write_palette()
1463 if (++s->vga.dac_sub_index == 3) { in cirrus_vga_write_palette()
1464 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { in cirrus_vga_write_palette()
1465 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], in cirrus_vga_write_palette()
1466 s->vga.dac_cache, 3); in cirrus_vga_write_palette()
1468 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); in cirrus_vga_write_palette()
1471 s->vga.dac_sub_index = 0; in cirrus_vga_write_palette()
1472 s->vga.dac_write_index++; in cirrus_vga_write_palette()
1478 * I/O access between 0x3ce-0x3cf
1485 case 0x00: // Standard VGA, BGCOLOR 0x000000ff in cirrus_vga_read_gr()
1486 return s->cirrus_shadow_gr0; in cirrus_vga_read_gr()
1487 case 0x01: // Standard VGA, FGCOLOR 0x000000ff in cirrus_vga_read_gr()
1488 return s->cirrus_shadow_gr1; in cirrus_vga_read_gr()
1489 case 0x02: // Standard VGA in cirrus_vga_read_gr()
1490 case 0x03: // Standard VGA in cirrus_vga_read_gr()
1491 case 0x04: // Standard VGA in cirrus_vga_read_gr()
1492 case 0x06: // Standard VGA in cirrus_vga_read_gr()
1493 case 0x07: // Standard VGA in cirrus_vga_read_gr()
1494 case 0x08: // Standard VGA in cirrus_vga_read_gr()
1495 return s->vga.gr[s->vga.gr_index]; in cirrus_vga_read_gr()
1496 case 0x05: // Standard VGA, Cirrus extended mode in cirrus_vga_read_gr()
1502 return s->vga.gr[reg_index]; in cirrus_vga_read_gr()
1515 case 0x00: // Standard VGA, BGCOLOR 0x000000ff in cirrus_vga_write_gr()
1516 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1517 s->cirrus_shadow_gr0 = reg_value; in cirrus_vga_write_gr()
1519 case 0x01: // Standard VGA, FGCOLOR 0x000000ff in cirrus_vga_write_gr()
1520 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1521 s->cirrus_shadow_gr1 = reg_value; in cirrus_vga_write_gr()
1523 case 0x02: // Standard VGA in cirrus_vga_write_gr()
1524 case 0x03: // Standard VGA in cirrus_vga_write_gr()
1525 case 0x04: // Standard VGA in cirrus_vga_write_gr()
1526 case 0x06: // Standard VGA in cirrus_vga_write_gr()
1527 case 0x07: // Standard VGA in cirrus_vga_write_gr()
1528 case 0x08: // Standard VGA in cirrus_vga_write_gr()
1529 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1531 case 0x05: // Standard VGA, Cirrus extended mode in cirrus_vga_write_gr()
1532 s->vga.gr[reg_index] = reg_value & 0x7f; in cirrus_vga_write_gr()
1537 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1543 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1563 case 0x30: // BLT MODE in cirrus_vga_write_gr()
1570 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1576 s->vga.gr[reg_index] = reg_value & 0x1f; in cirrus_vga_write_gr()
1579 s->vga.gr[reg_index] = reg_value & 0x3f; in cirrus_vga_write_gr()
1580 /* if auto start mode, starts bit blt now */ in cirrus_vga_write_gr()
1581 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { in cirrus_vga_write_gr()
1586 s->vga.gr[reg_index] = reg_value & 0x3f; in cirrus_vga_write_gr()
1601 * I/O access between 0x3d4-0x3d5
1608 case 0x00: // Standard VGA in cirrus_vga_read_cr()
1609 case 0x01: // Standard VGA in cirrus_vga_read_cr()
1610 case 0x02: // Standard VGA in cirrus_vga_read_cr()
1611 case 0x03: // Standard VGA in cirrus_vga_read_cr()
1612 case 0x04: // Standard VGA in cirrus_vga_read_cr()
1613 case 0x05: // Standard VGA in cirrus_vga_read_cr()
1614 case 0x06: // Standard VGA in cirrus_vga_read_cr()
1615 case 0x07: // Standard VGA in cirrus_vga_read_cr()
1616 case 0x08: // Standard VGA in cirrus_vga_read_cr()
1617 case 0x09: // Standard VGA in cirrus_vga_read_cr()
1618 case 0x0a: // Standard VGA in cirrus_vga_read_cr()
1619 case 0x0b: // Standard VGA in cirrus_vga_read_cr()
1620 case 0x0c: // Standard VGA in cirrus_vga_read_cr()
1621 case 0x0d: // Standard VGA in cirrus_vga_read_cr()
1622 case 0x0e: // Standard VGA in cirrus_vga_read_cr()
1623 case 0x0f: // Standard VGA in cirrus_vga_read_cr()
1624 case 0x10: // Standard VGA in cirrus_vga_read_cr()
1625 case 0x11: // Standard VGA in cirrus_vga_read_cr()
1626 case 0x12: // Standard VGA in cirrus_vga_read_cr()
1627 case 0x13: // Standard VGA in cirrus_vga_read_cr()
1628 case 0x14: // Standard VGA in cirrus_vga_read_cr()
1629 case 0x15: // Standard VGA in cirrus_vga_read_cr()
1630 case 0x16: // Standard VGA in cirrus_vga_read_cr()
1631 case 0x17: // Standard VGA in cirrus_vga_read_cr()
1632 case 0x18: // Standard VGA in cirrus_vga_read_cr()
1633 return s->vga.cr[s->vga.cr_index]; in cirrus_vga_read_cr()
1635 return (s->vga.ar_flip_flop << 7); in cirrus_vga_read_cr()
1644 return s->vga.cr[s->vga.cr_index]; in cirrus_vga_read_cr()
1646 return s->vga.ar_index & 0x3f; in cirrus_vga_read_cr()
1656 switch (s->vga.cr_index) { in cirrus_vga_write_cr()
1657 case 0x00: // Standard VGA in cirrus_vga_write_cr()
1658 case 0x01: // Standard VGA in cirrus_vga_write_cr()
1659 case 0x02: // Standard VGA in cirrus_vga_write_cr()
1660 case 0x03: // Standard VGA in cirrus_vga_write_cr()
1661 case 0x04: // Standard VGA in cirrus_vga_write_cr()
1662 case 0x05: // Standard VGA in cirrus_vga_write_cr()
1663 case 0x06: // Standard VGA in cirrus_vga_write_cr()
1664 case 0x07: // Standard VGA in cirrus_vga_write_cr()
1665 case 0x08: // Standard VGA in cirrus_vga_write_cr()
1666 case 0x09: // Standard VGA in cirrus_vga_write_cr()
1667 case 0x0a: // Standard VGA in cirrus_vga_write_cr()
1668 case 0x0b: // Standard VGA in cirrus_vga_write_cr()
1669 case 0x0c: // Standard VGA in cirrus_vga_write_cr()
1670 case 0x0d: // Standard VGA in cirrus_vga_write_cr()
1671 case 0x0e: // Standard VGA in cirrus_vga_write_cr()
1672 case 0x0f: // Standard VGA in cirrus_vga_write_cr()
1673 case 0x10: // Standard VGA in cirrus_vga_write_cr()
1674 case 0x11: // Standard VGA in cirrus_vga_write_cr()
1675 case 0x12: // Standard VGA in cirrus_vga_write_cr()
1676 case 0x13: // Standard VGA in cirrus_vga_write_cr()
1677 case 0x14: // Standard VGA in cirrus_vga_write_cr()
1678 case 0x15: // Standard VGA in cirrus_vga_write_cr()
1679 case 0x16: // Standard VGA in cirrus_vga_write_cr()
1680 case 0x17: // Standard VGA in cirrus_vga_write_cr()
1681 case 0x18: // Standard VGA in cirrus_vga_write_cr()
1682 /* handle CR0-7 protection */ in cirrus_vga_write_cr()
1683 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { in cirrus_vga_write_cr()
1685 if (s->vga.cr_index == 7) in cirrus_vga_write_cr()
1686 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); in cirrus_vga_write_cr()
1689 s->vga.cr[s->vga.cr_index] = reg_value; in cirrus_vga_write_cr()
1690 switch(s->vga.cr_index) { in cirrus_vga_write_cr()
1698 s->vga.update_retrace_info(&s->vga); in cirrus_vga_write_cr()
1707 s->vga.cr[s->vga.cr_index] = reg_value; in cirrus_vga_write_cr()
1710 s->vga.cr_index, reg_value); in cirrus_vga_write_cr()
1722 s->vga.cr_index, reg_value); in cirrus_vga_write_cr()
1729 * memory-mapped I/O (bitblt)
1833 "cirrus: mmio read - address 0x%04x\n", address); in cirrus_mmio_blt_read()
1944 "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", in cirrus_mmio_blt_write()
1952 * write mode 4/5
1957 unsigned mode, in cirrus_mem_writeb_mode4and5_8bpp() argument
1966 dst = s->vga.vram_ptr + ((offset + x) & s->cirrus_addr_mask); in cirrus_mem_writeb_mode4and5_8bpp()
1968 *dst = s->cirrus_shadow_gr1; in cirrus_mem_writeb_mode4and5_8bpp()
1969 } else if (mode == 5) { in cirrus_mem_writeb_mode4and5_8bpp()
1970 *dst = s->cirrus_shadow_gr0; in cirrus_mem_writeb_mode4and5_8bpp()
1974 memory_region_set_dirty(&s->vga.vram, offset, 8); in cirrus_mem_writeb_mode4and5_8bpp()
1978 unsigned mode, in cirrus_mem_writeb_mode4and5_16bpp() argument
1987 dst = s->vga.vram_ptr + ((offset + 2 * x) & s->cirrus_addr_mask & ~1); in cirrus_mem_writeb_mode4and5_16bpp()
1989 *dst = s->cirrus_shadow_gr1; in cirrus_mem_writeb_mode4and5_16bpp()
1990 *(dst + 1) = s->vga.gr[0x11]; in cirrus_mem_writeb_mode4and5_16bpp()
1991 } else if (mode == 5) { in cirrus_mem_writeb_mode4and5_16bpp()
1992 *dst = s->cirrus_shadow_gr0; in cirrus_mem_writeb_mode4and5_16bpp()
1993 *(dst + 1) = s->vga.gr[0x10]; in cirrus_mem_writeb_mode4and5_16bpp()
1997 memory_region_set_dirty(&s->vga.vram, offset, 16); in cirrus_mem_writeb_mode4and5_16bpp()
2002 * memory access between 0xa0000-0xbffff
2015 if ((s->vga.sr[0x07] & 0x01) == 0) { in cirrus_vga_mem_read()
2016 return vga_mem_readb(&s->vga, addr); in cirrus_vga_mem_read()
2024 if (bank_offset < s->cirrus_bank_limit[bank_index]) { in cirrus_vga_mem_read()
2025 bank_offset += s->cirrus_bank_base[bank_index]; in cirrus_vga_mem_read()
2026 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_vga_mem_read()
2028 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_vga_mem_read()
2031 bank_offset &= s->cirrus_addr_mask; in cirrus_vga_mem_read()
2032 val = *(s->vga.vram_ptr + bank_offset); in cirrus_vga_mem_read()
2036 /* memory-mapped I/O */ in cirrus_vga_mem_read()
2038 if ((s->vga.sr[0x17] & 0x44) == 0x04) { in cirrus_vga_mem_read()
2057 unsigned mode; in cirrus_vga_mem_write() local
2059 if ((s->vga.sr[0x07] & 0x01) == 0) { in cirrus_vga_mem_write()
2060 vga_mem_writeb(&s->vga, addr, mem_value); in cirrus_vga_mem_write()
2065 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { in cirrus_vga_mem_write()
2067 *s->cirrus_srcptr++ = (uint8_t) mem_value; in cirrus_vga_mem_write()
2068 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { in cirrus_vga_mem_write()
2075 if (bank_offset < s->cirrus_bank_limit[bank_index]) { in cirrus_vga_mem_write()
2076 bank_offset += s->cirrus_bank_base[bank_index]; in cirrus_vga_mem_write()
2077 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_vga_mem_write()
2079 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_vga_mem_write()
2082 bank_offset &= s->cirrus_addr_mask; in cirrus_vga_mem_write()
2083 mode = s->vga.gr[0x05] & 0x7; in cirrus_vga_mem_write()
2084 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_vga_mem_write()
2085 *(s->vga.vram_ptr + bank_offset) = mem_value; in cirrus_vga_mem_write()
2086 memory_region_set_dirty(&s->vga.vram, bank_offset, in cirrus_vga_mem_write()
2089 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { in cirrus_vga_mem_write()
2090 cirrus_mem_writeb_mode4and5_8bpp(s, mode, in cirrus_vga_mem_write()
2094 cirrus_mem_writeb_mode4and5_16bpp(s, mode, in cirrus_vga_mem_write()
2102 /* memory-mapped I/O */ in cirrus_vga_mem_write()
2103 if ((s->vga.sr[0x17] & 0x44) == 0x04) { in cirrus_vga_mem_write()
2131 if (s->last_hw_cursor_size) { in invalidate_cursor1()
2132 vga_invalidate_scanlines(&s->vga, in invalidate_cursor1()
2133 s->last_hw_cursor_y + s->last_hw_cursor_y_start, in invalidate_cursor1()
2134 s->last_hw_cursor_y + s->last_hw_cursor_y_end); in invalidate_cursor1()
2144 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB; in cirrus_cursor_compute_yrange()
2145 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_compute_yrange()
2146 src += (s->vga.sr[0x13] & 0x3c) * 256; in cirrus_cursor_compute_yrange()
2148 y_max = -1; in cirrus_cursor_compute_yrange()
2163 src += (s->vga.sr[0x13] & 0x3f) * 256; in cirrus_cursor_compute_yrange()
2165 y_max = -1; in cirrus_cursor_compute_yrange()
2179 s->last_hw_cursor_y_start = 0; in cirrus_cursor_compute_yrange()
2180 s->last_hw_cursor_y_end = 0; in cirrus_cursor_compute_yrange()
2182 s->last_hw_cursor_y_start = y_min; in cirrus_cursor_compute_yrange()
2183 s->last_hw_cursor_y_end = y_max + 1; in cirrus_cursor_compute_yrange()
2194 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { in cirrus_cursor_invalidate()
2197 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) in cirrus_cursor_invalidate()
2203 if (s->last_hw_cursor_size != size || in cirrus_cursor_invalidate()
2204 s->last_hw_cursor_x != s->vga.hw_cursor_x || in cirrus_cursor_invalidate()
2205 s->last_hw_cursor_y != s->vga.hw_cursor_y) { in cirrus_cursor_invalidate()
2209 s->last_hw_cursor_size = size; in cirrus_cursor_invalidate()
2210 s->last_hw_cursor_x = s->vga.hw_cursor_x; in cirrus_cursor_invalidate()
2211 s->last_hw_cursor_y = s->vga.hw_cursor_y; in cirrus_cursor_invalidate()
2233 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1; in vga_draw_cursor_line()
2234 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1; in vga_draw_cursor_line()
2260 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) in cirrus_cursor_draw_line()
2263 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_draw_line()
2268 if (scr_y < s->vga.hw_cursor_y || in cirrus_cursor_draw_line()
2269 scr_y >= (s->vga.hw_cursor_y + h)) { in cirrus_cursor_draw_line()
2273 src = s->vga.vram_ptr + s->real_vram_size - 16 * KiB; in cirrus_cursor_draw_line()
2274 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { in cirrus_cursor_draw_line()
2275 src += (s->vga.sr[0x13] & 0x3c) * 256; in cirrus_cursor_draw_line()
2276 src += (scr_y - s->vga.hw_cursor_y) * 16; in cirrus_cursor_draw_line()
2283 src += (s->vga.sr[0x13] & 0x3f) * 256; in cirrus_cursor_draw_line()
2284 src += (scr_y - s->vga.hw_cursor_y) * 4; in cirrus_cursor_draw_line()
2296 x1 = s->vga.hw_cursor_x; in cirrus_cursor_draw_line()
2297 if (x1 >= s->vga.last_scr_width) in cirrus_cursor_draw_line()
2299 x2 = s->vga.hw_cursor_x + w; in cirrus_cursor_draw_line()
2300 if (x2 > s->vga.last_scr_width) in cirrus_cursor_draw_line()
2301 x2 = s->vga.last_scr_width; in cirrus_cursor_draw_line()
2302 w = x2 - x1; in cirrus_cursor_draw_line()
2303 palette = s->cirrus_hidden_palette; in cirrus_cursor_draw_line()
2326 addr &= s->cirrus_addr_mask; in cirrus_linear_read()
2328 if (((s->vga.sr[0x17] & 0x44) == 0x44) && in cirrus_linear_read()
2329 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { in cirrus_linear_read()
2330 /* memory-mapped I/O */ in cirrus_linear_read()
2337 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_linear_read()
2339 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_linear_read()
2342 addr &= s->cirrus_addr_mask; in cirrus_linear_read()
2343 ret = *(s->vga.vram_ptr + addr); in cirrus_linear_read()
2353 unsigned mode; in cirrus_linear_write() local
2355 addr &= s->cirrus_addr_mask; in cirrus_linear_write()
2357 if (((s->vga.sr[0x17] & 0x44) == 0x44) && in cirrus_linear_write()
2358 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { in cirrus_linear_write()
2359 /* memory-mapped I/O */ in cirrus_linear_write()
2361 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { in cirrus_linear_write()
2363 *s->cirrus_srcptr++ = (uint8_t) val; in cirrus_linear_write()
2364 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { in cirrus_linear_write()
2369 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_linear_write()
2371 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_linear_write()
2374 addr &= s->cirrus_addr_mask; in cirrus_linear_write()
2376 mode = s->vga.gr[0x05] & 0x7; in cirrus_linear_write()
2377 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_linear_write()
2378 *(s->vga.vram_ptr + addr) = (uint8_t) val; in cirrus_linear_write()
2379 memory_region_set_dirty(&s->vga.vram, addr, 1); in cirrus_linear_write()
2381 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { in cirrus_linear_write()
2382 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); in cirrus_linear_write()
2384 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); in cirrus_linear_write()
2418 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { in cirrus_linear_bitblt_write()
2420 *s->cirrus_srcptr++ = (uint8_t) val; in cirrus_linear_bitblt_write()
2421 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { in cirrus_linear_bitblt_write()
2439 MemoryRegion *mr = &s->cirrus_bank[bank]; in map_linear_vram_bank()
2440 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end) in map_linear_vram_bank()
2441 && !((s->vga.sr[0x07] & 0x01) == 0) in map_linear_vram_bank()
2442 && !((s->vga.gr[0x0B] & 0x14) == 0x14) in map_linear_vram_bank()
2443 && !(s->vga.gr[0x0B] & 0x02); in map_linear_vram_bank()
2446 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); in map_linear_vram_bank()
2451 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) { in map_linear_vram()
2452 s->linear_vram = true; in map_linear_vram()
2453 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); in map_linear_vram()
2461 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) { in unmap_linear_vram()
2462 s->linear_vram = false; in unmap_linear_vram()
2463 memory_region_del_subregion(&s->pci_bar, &s->vga.vram); in unmap_linear_vram()
2465 memory_region_set_enabled(&s->cirrus_bank[0], false); in unmap_linear_vram()
2466 memory_region_set_enabled(&s->cirrus_bank[1], false); in unmap_linear_vram()
2472 unsigned mode; in cirrus_update_memory_access() local
2475 if ((s->vga.sr[0x17] & 0x44) == 0x44) { in cirrus_update_memory_access()
2477 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { in cirrus_update_memory_access()
2480 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { in cirrus_update_memory_access()
2482 } else if (s->vga.gr[0x0B] & 0x02) { in cirrus_update_memory_access()
2486 mode = s->vga.gr[0x05] & 0x7; in cirrus_update_memory_access()
2487 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { in cirrus_update_memory_access()
2504 VGACommonState *s = &c->vga; in cirrus_vga_ioport_read()
2514 if (s->ar_flip_flop == 0) { in cirrus_vga_ioport_read()
2515 val = s->ar_index; in cirrus_vga_ioport_read()
2521 index = s->ar_index & 0x1f; in cirrus_vga_ioport_read()
2523 val = s->ar[index]; in cirrus_vga_ioport_read()
2528 val = s->st00; in cirrus_vga_ioport_read()
2531 val = s->sr_index; in cirrus_vga_ioport_read()
2541 val = s->dac_state; in cirrus_vga_ioport_read()
2544 val = s->dac_write_index; in cirrus_vga_ioport_read()
2545 c->cirrus_hidden_dac_lockindex = 0; in cirrus_vga_ioport_read()
2551 val = s->fcr; in cirrus_vga_ioport_read()
2554 val = s->msr; in cirrus_vga_ioport_read()
2557 val = s->gr_index; in cirrus_vga_ioport_read()
2560 val = cirrus_vga_read_gr(c, s->gr_index); in cirrus_vga_ioport_read()
2564 val = s->cr_index; in cirrus_vga_ioport_read()
2568 val = cirrus_vga_read_cr(c, s->cr_index); in cirrus_vga_ioport_read()
2573 val = s->st01 = s->retrace(s); in cirrus_vga_ioport_read()
2574 s->ar_flip_flop = 0; in cirrus_vga_ioport_read()
2589 VGACommonState *s = &c->vga; in cirrus_vga_ioport_write()
2594 /* check port range access depending on color/monochrome mode */ in cirrus_vga_ioport_write()
2602 if (s->ar_flip_flop == 0) { in cirrus_vga_ioport_write()
2604 s->ar_index = val; in cirrus_vga_ioport_write()
2606 index = s->ar_index & 0x1f; in cirrus_vga_ioport_write()
2609 s->ar[index] = val & 0x3f; in cirrus_vga_ioport_write()
2612 s->ar[index] = val & ~0x10; in cirrus_vga_ioport_write()
2615 s->ar[index] = val; in cirrus_vga_ioport_write()
2618 s->ar[index] = val & ~0xc0; in cirrus_vga_ioport_write()
2621 s->ar[index] = val & ~0xf0; in cirrus_vga_ioport_write()
2624 s->ar[index] = val & ~0xf0; in cirrus_vga_ioport_write()
2630 s->ar_flip_flop ^= 1; in cirrus_vga_ioport_write()
2633 s->msr = val & ~0x10; in cirrus_vga_ioport_write()
2634 s->update_retrace_info(s); in cirrus_vga_ioport_write()
2637 s->sr_index = val; in cirrus_vga_ioport_write()
2646 s->dac_read_index = val; in cirrus_vga_ioport_write()
2647 s->dac_sub_index = 0; in cirrus_vga_ioport_write()
2648 s->dac_state = 3; in cirrus_vga_ioport_write()
2651 s->dac_write_index = val; in cirrus_vga_ioport_write()
2652 s->dac_sub_index = 0; in cirrus_vga_ioport_write()
2653 s->dac_state = 0; in cirrus_vga_ioport_write()
2659 s->gr_index = val; in cirrus_vga_ioport_write()
2662 cirrus_vga_write_gr(c, s->gr_index, val); in cirrus_vga_ioport_write()
2666 s->cr_index = val; in cirrus_vga_ioport_write()
2674 s->fcr = val & 0x10; in cirrus_vga_ioport_write()
2681 * memory-mapped I/O access
2691 return cirrus_mmio_blt_read(s, addr - 0x100); in cirrus_mmio_read()
2703 cirrus_mmio_blt_write(s, addr - 0x100, val); in cirrus_mmio_write()
2725 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; in cirrus_post_load()
2726 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; in cirrus_post_load()
2732 s->vga.graphic_mode = -1; in cirrus_post_load()
2770 /* XXX: we do not save the bitblt state - we assume we do not save
2798 vga_common_reset(&s->vga); in cirrus_reset()
2800 s->vga.sr[0x06] = 0x0f; in cirrus_reset()
2801 if (s->device_id == CIRRUS_ID_CLGD5446) { in cirrus_reset()
2803 s->vga.sr[0x1F] = 0x2d; // MemClock in cirrus_reset()
2804 s->vga.gr[0x18] = 0x0f; // fastest memory configuration in cirrus_reset()
2805 s->vga.sr[0x0f] = 0x98; in cirrus_reset()
2806 s->vga.sr[0x17] = 0x20; in cirrus_reset()
2807 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ in cirrus_reset()
2809 s->vga.sr[0x1F] = 0x22; // MemClock in cirrus_reset()
2810 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M; in cirrus_reset()
2811 s->vga.sr[0x17] = s->bustype; in cirrus_reset()
2812 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ in cirrus_reset()
2814 s->vga.cr[0x27] = s->device_id; in cirrus_reset()
2816 s->cirrus_hidden_dac_lockindex = 5; in cirrus_reset()
2817 s->cirrus_hidden_dac_data = 0; in cirrus_reset()
2867 s->device_id = device_id; in cirrus_init_common()
2869 s->bustype = CIRRUS_BUSTYPE_PCI; in cirrus_init_common()
2871 s->bustype = CIRRUS_BUSTYPE_ISA; in cirrus_init_common()
2874 /* Register ioport 0x3b0 - 0x3df */ in cirrus_init_common()
2875 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s, in cirrus_init_common()
2876 "cirrus-io", 0x30); in cirrus_init_common()
2877 memory_region_set_flush_coalesced(&s->cirrus_vga_io); in cirrus_init_common()
2878 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io); in cirrus_init_common()
2880 memory_region_init(&s->low_mem_container, owner, in cirrus_init_common()
2881 "cirrus-lowmem-container", in cirrus_init_common()
2884 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s, in cirrus_init_common()
2885 "cirrus-low-memory", 0x20000); in cirrus_init_common()
2886 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem); in cirrus_init_common()
2889 MemoryRegion *bank = &s->cirrus_bank[i]; in cirrus_init_common()
2890 memory_region_init_alias(bank, owner, names[i], &s->vga.vram, in cirrus_init_common()
2893 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000, in cirrus_init_common()
2898 &s->low_mem_container, in cirrus_init_common()
2900 memory_region_set_coalescing(&s->low_mem); in cirrus_init_common()
2903 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s, in cirrus_init_common()
2904 "cirrus-linear-io", s->vga.vram_size_mb * MiB); in cirrus_init_common()
2905 memory_region_set_flush_coalesced(&s->cirrus_linear_io); in cirrus_init_common()
2908 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner, in cirrus_init_common()
2911 "cirrus-bitblt-mmio", in cirrus_init_common()
2913 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io); in cirrus_init_common()
2915 /* I/O handler for memory-mapped I/O */ in cirrus_init_common()
2916 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s, in cirrus_init_common()
2917 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE); in cirrus_init_common()
2918 memory_region_set_flush_coalesced(&s->cirrus_mmio_io); in cirrus_init_common()
2920 s->real_vram_size = in cirrus_init_common()
2921 (s->device_id == CIRRUS_ID_CLGD5446) ? 4 * MiB : 2 * MiB; in cirrus_init_common()
2923 /* XXX: s->vga.vram_size must be a power of two */ in cirrus_init_common()
2924 s->cirrus_addr_mask = s->real_vram_size - 1; in cirrus_init_common()
2925 s->linear_mmio_mask = s->real_vram_size - 256; in cirrus_init_common()
2927 s->vga.get_bpp = cirrus_get_bpp; in cirrus_init_common()
2928 s->vga.get_params = cirrus_get_params; in cirrus_init_common()
2929 s->vga.get_resolution = cirrus_get_resolution; in cirrus_init_common()
2930 s->vga.cursor_invalidate = cirrus_cursor_invalidate; in cirrus_init_common()
2931 s->vga.cursor_draw_line = cirrus_cursor_draw_line; in cirrus_init_common()
2945 CirrusVGAState *s = &d->cirrus_vga; in pci_cirrus_vga_realize()
2947 int16_t device_id = pc->device_id; in pci_cirrus_vga_realize()
2953 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 && in pci_cirrus_vga_realize()
2954 s->vga.vram_size_mb != 16) { in pci_cirrus_vga_realize()
2956 s->vga.vram_size_mb); in pci_cirrus_vga_realize()
2960 if (!vga_common_init(&s->vga, OBJECT(dev), errp)) { in pci_cirrus_vga_realize()
2965 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga); in pci_cirrus_vga_realize()
2968 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000); in pci_cirrus_vga_realize()
2971 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io); in pci_cirrus_vga_realize()
2972 memory_region_add_subregion(&s->pci_bar, 0x1000000, in pci_cirrus_vga_realize()
2973 &s->cirrus_linear_bitblt_io); in pci_cirrus_vga_realize()
2977 /* memory #1 memory-mapped I/O */ in pci_cirrus_vga_realize()
2978 /* XXX: s->vga.vram_size must be a power of two */ in pci_cirrus_vga_realize()
2979 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar); in pci_cirrus_vga_realize()
2981 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); in pci_cirrus_vga_realize()
2990 DEFINE_PROP_BOOL("global-vmstate", struct PCICirrusVGAState,
3000 k->realize = pci_cirrus_vga_realize; in cirrus_vga_class_init()
3001 k->romfile = VGABIOS_CIRRUS_FILENAME; in cirrus_vga_class_init()
3002 k->vendor_id = PCI_VENDOR_ID_CIRRUS; in cirrus_vga_class_init()
3003 k->device_id = CIRRUS_ID_CLGD5446; in cirrus_vga_class_init()
3004 k->class_id = PCI_CLASS_DISPLAY_VGA; in cirrus_vga_class_init()
3005 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); in cirrus_vga_class_init()
3006 dc->desc = "Cirrus CLGD 54xx VGA"; in cirrus_vga_class_init()
3007 dc->vmsd = &vmstate_pci_cirrus_vga; in cirrus_vga_class_init()
3009 dc->hotpluggable = false; in cirrus_vga_class_init()