Lines Matching +full:lock +full:- +full:offset
7 * COPYING file in the top-level directory.
64 static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, in cxl_cache_mem_read_reg() argument
68 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_read_reg()
72 if (cregs->special_ops && cregs->special_ops->read) { in cxl_cache_mem_read_reg()
73 return cregs->special_ops->read(cxl_cstate, offset, 4); in cxl_cache_mem_read_reg()
75 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); in cxl_cache_mem_read_reg()
76 return cregs->cache_mem_registers[offset / 4]; in cxl_cache_mem_read_reg()
91 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, in dumb_hdm_handler() argument
94 ComponentRegisters *cregs = &cxl_cstate->crb; in dumb_hdm_handler()
95 uint32_t *cache_mem = cregs->cache_mem_registers; in dumb_hdm_handler()
99 switch (offset) { in dumb_hdm_handler()
118 stl_le_p((uint8_t *)cache_mem + offset, value); in dumb_hdm_handler()
121 static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, in cxl_cache_mem_write_reg() argument
125 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_write_reg()
130 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_regs_write_mask) != 4); in cxl_cache_mem_write_reg()
131 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); in cxl_cache_mem_write_reg()
132 mask = cregs->cache_mem_regs_write_mask[offset / 4]; in cxl_cache_mem_write_reg()
135 value |= ~mask & cregs->cache_mem_registers[offset / 4]; in cxl_cache_mem_write_reg()
136 if (cregs->special_ops && cregs->special_ops->write) { in cxl_cache_mem_write_reg()
137 cregs->special_ops->write(cxl_cstate, offset, value, size); in cxl_cache_mem_write_reg()
141 if (offset >= A_CXL_HDM_DECODER_CAPABILITY && in cxl_cache_mem_write_reg()
142 offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) { in cxl_cache_mem_write_reg()
143 dumb_hdm_handler(cxl_cstate, offset, value); in cxl_cache_mem_write_reg()
145 cregs->cache_mem_registers[offset / 4] = value; in cxl_cache_mem_write_reg()
194 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_component_register_block_init()
196 memory_region_init(&cregs->component_registers, obj, type, in cxl_component_register_block_init()
200 memory_region_init_io(&cregs->io, obj, NULL, NULL, ".io", in cxl_component_register_block_init()
202 memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, in cxl_component_register_block_init()
205 memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); in cxl_component_register_block_init()
206 memory_region_add_subregion(&cregs->component_registers, in cxl_component_register_block_init()
208 &cregs->cache_mem); in cxl_component_register_block_init()
219 /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ in ras_init_common()
236 int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO; in hdm_init_common()
371 * for tracking the valid offset.
381 PCIDevice *pdev = cxl->pdev; in cxl_component_create_dvsec()
382 uint16_t offset = cxl->dvsec_offset; in cxl_component_create_dvsec() local
383 uint8_t *wmask = pdev->wmask; in cxl_component_create_dvsec()
385 assert(offset >= PCI_CFG_SPACE_SIZE && in cxl_component_create_dvsec()
386 ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); in cxl_component_create_dvsec()
391 pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); in cxl_component_create_dvsec()
392 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, in cxl_component_create_dvsec()
394 pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); in cxl_component_create_dvsec()
395 memcpy(pdev->config + offset + sizeof(DVSECHeader), in cxl_component_create_dvsec()
397 length - sizeof(DVSECHeader)); in cxl_component_create_dvsec()
402 /* Cntrl RW Lock - so needs explicit blocking when lock is set */ in cxl_component_create_dvsec()
403 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; in cxl_component_create_dvsec()
404 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; in cxl_component_create_dvsec()
406 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; in cxl_component_create_dvsec()
407 /* Lock is RW Once */ in cxl_component_create_dvsec()
408 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; in cxl_component_create_dvsec()
409 /* range1/2_base_high/low is RW Lock */ in cxl_component_create_dvsec()
410 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; in cxl_component_create_dvsec()
411 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; in cxl_component_create_dvsec()
412 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; in cxl_component_create_dvsec()
413 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; in cxl_component_create_dvsec()
414 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; in cxl_component_create_dvsec()
415 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; in cxl_component_create_dvsec()
416 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; in cxl_component_create_dvsec()
417 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; in cxl_component_create_dvsec()
418 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; in cxl_component_create_dvsec()
419 wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; in cxl_component_create_dvsec()
424 wmask[offset + offsetof(CXLDVSECPortExt, control)] = 0x0F; in cxl_component_create_dvsec()
425 wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] = 0x40; in cxl_component_create_dvsec()
426 wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] = 0xFF; in cxl_component_create_dvsec()
427 wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_limit)] = 0xFF; in cxl_component_create_dvsec()
428 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base)] = 0xF0; in cxl_component_create_dvsec()
429 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base) + 1] = 0xFF; in cxl_component_create_dvsec()
430 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit)] = 0xF0; in cxl_component_create_dvsec()
431 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit) + 1] = 0xFF; in cxl_component_create_dvsec()
432 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base)] = 0xF0; in cxl_component_create_dvsec()
433 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base) + 1] = 0xFF; in cxl_component_create_dvsec()
434 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit)] = 0xF0; in cxl_component_create_dvsec()
435 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit) + 1] = in cxl_component_create_dvsec()
437 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high)] = in cxl_component_create_dvsec()
439 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 1] = in cxl_component_create_dvsec()
441 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 2] = in cxl_component_create_dvsec()
443 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 3] = in cxl_component_create_dvsec()
445 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high)] = in cxl_component_create_dvsec()
447 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 1] = in cxl_component_create_dvsec()
449 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 2] = in cxl_component_create_dvsec()
451 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 3] = in cxl_component_create_dvsec()
455 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; in cxl_component_create_dvsec()
456 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; in cxl_component_create_dvsec()
457 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; in cxl_component_create_dvsec()
458 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; in cxl_component_create_dvsec()
461 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; in cxl_component_create_dvsec()
462 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; in cxl_component_create_dvsec()
463 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; in cxl_component_create_dvsec()
464 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; in cxl_component_create_dvsec()
465 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; in cxl_component_create_dvsec()
466 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; in cxl_component_create_dvsec()
472 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; in cxl_component_create_dvsec()
475 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; in cxl_component_create_dvsec()
485 range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); in cxl_component_create_dvsec()
486 cxl->dvsec_offset += length; in cxl_component_create_dvsec()