Lines Matching +full:stop +full:- +full:mode
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
22 #include "chardev/char-fe.h"
23 #include "chardev/char-serial.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */
61 FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */
68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */
69 FIELD(CR2, STOP, 12, 2) /* STOP bits */
76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */
80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */
81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */
82 FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */
83 FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */
85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */
94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */
96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */
97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */
98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */
111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */
118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
159 if (s->cr1 & R_CR1_TE_MASK) { in stm32l4x5_update_isr()
160 s->isr |= R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
162 s->isr &= ~R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
165 if (s->cr1 & R_CR1_RE_MASK) { in stm32l4x5_update_isr()
166 s->isr |= R_ISR_REACK_MASK; in stm32l4x5_update_isr()
168 s->isr &= ~R_ISR_REACK_MASK; in stm32l4x5_update_isr()
174 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || in stm32l4x5_update_irq()
175 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || in stm32l4x5_update_irq()
176 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
177 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || in stm32l4x5_update_irq()
178 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || in stm32l4x5_update_irq()
179 ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || in stm32l4x5_update_irq()
180 ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || in stm32l4x5_update_irq()
181 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || in stm32l4x5_update_irq()
182 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || in stm32l4x5_update_irq()
183 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
184 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || in stm32l4x5_update_irq()
185 ((s->isr & R_ISR_ORE_MASK) && in stm32l4x5_update_irq()
186 ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || in stm32l4x5_update_irq()
188 ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || in stm32l4x5_update_irq()
189 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { in stm32l4x5_update_irq()
190 qemu_irq_raise(s->irq); in stm32l4x5_update_irq()
191 trace_stm32l4x5_usart_irq_raised(s->isr); in stm32l4x5_update_irq()
193 qemu_irq_lower(s->irq); in stm32l4x5_update_irq()
202 if (!(s->isr & R_ISR_RXNE_MASK)) { in stm32l4x5_usart_base_can_receive()
214 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { in stm32l4x5_usart_base_receive()
216 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); in stm32l4x5_usart_base_receive()
221 if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { in stm32l4x5_usart_base_receive()
226 s->isr |= R_ISR_ORE_MASK; in stm32l4x5_usart_base_receive()
227 trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); in stm32l4x5_usart_base_receive()
230 s->rdr = *buf; in stm32l4x5_usart_base_receive()
231 s->isr |= R_ISR_RXNE_MASK; in stm32l4x5_usart_base_receive()
232 trace_stm32l4x5_usart_rx(s->rdr); in stm32l4x5_usart_base_receive()
248 uint8_t ch = s->tdr; in usart_transmit()
250 s->watch_tag = 0; in usart_transmit()
252 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { in usart_transmit()
256 ret = qemu_chr_fe_write(&s->chr, &ch, 1); in usart_transmit()
258 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in usart_transmit()
260 if (!s->watch_tag) { in usart_transmit()
263 * just insta-drain the buffer, so the serial output in usart_transmit()
276 s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; in usart_transmit()
283 if (s->watch_tag) { in usart_cancel_transmit()
284 g_source_remove(s->watch_tag); in usart_cancel_transmit()
285 s->watch_tag = 0; in usart_cancel_transmit()
296 if (s->cr1 & R_CR1_PCE_MASK) { in stm32l4x5_update_params()
297 if (s->cr1 & R_CR1_PS_MASK) { in stm32l4x5_update_params()
306 /* Select the number of stop bits */ in stm32l4x5_update_params()
307 switch (FIELD_EX32(s->cr2, CR2, STOP)) { in stm32l4x5_update_params()
316 "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u", in stm32l4x5_update_params()
317 FIELD_EX32(s->cr2, CR2, STOP)); in stm32l4x5_update_params()
322 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { in stm32l4x5_update_params()
339 value = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_update_params()
346 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { in stm32l4x5_update_params()
355 * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. in stm32l4x5_update_params()
356 * - BRR[3] must be kept cleared. in stm32l4x5_update_params()
357 * - BRR[15:4] = USARTDIV[15:4] in stm32l4x5_update_params()
358 * - The frequency is multiplied by 2 in stm32l4x5_update_params()
363 speed = clock_get_hz(s->clk) / usart_div; in stm32l4x5_update_params()
370 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in stm32l4x5_update_params()
379 s->cr1 = 0x00000000; in stm32l4x5_usart_base_reset_hold()
380 s->cr2 = 0x00000000; in stm32l4x5_usart_base_reset_hold()
381 s->cr3 = 0x00000000; in stm32l4x5_usart_base_reset_hold()
382 s->brr = 0x00000000; in stm32l4x5_usart_base_reset_hold()
383 s->gtpr = 0x00000000; in stm32l4x5_usart_base_reset_hold()
384 s->rtor = 0x00000000; in stm32l4x5_usart_base_reset_hold()
385 s->isr = 0x020000C0; in stm32l4x5_usart_base_reset_hold()
386 s->rdr = 0x00000000; in stm32l4x5_usart_base_reset_hold()
387 s->tdr = 0x00000000; in stm32l4x5_usart_base_reset_hold()
398 s->isr &= ~R_ISR_RXNE_MASK; in usart_update_rqr()
414 retvalue = s->cr1; in stm32l4x5_usart_base_read()
417 retvalue = s->cr2; in stm32l4x5_usart_base_read()
420 retvalue = s->cr3; in stm32l4x5_usart_base_read()
423 retvalue = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_usart_base_read()
426 retvalue = s->gtpr; in stm32l4x5_usart_base_read()
429 retvalue = s->rtor; in stm32l4x5_usart_base_read()
436 retvalue = s->isr; in stm32l4x5_usart_base_read()
443 retvalue = FIELD_EX32(s->rdr, RDR, RDR); in stm32l4x5_usart_base_read()
445 s->isr &= ~R_ISR_RXNE_MASK; in stm32l4x5_usart_base_read()
449 retvalue = FIELD_EX32(s->tdr, TDR, TDR); in stm32l4x5_usart_base_read()
472 s->cr1 = value; in stm32l4x5_usart_base_write()
478 s->cr2 = value; in stm32l4x5_usart_base_write()
482 s->cr3 = value; in stm32l4x5_usart_base_write()
485 s->brr = value; in stm32l4x5_usart_base_write()
489 s->gtpr = value; in stm32l4x5_usart_base_write()
492 s->rtor = value; in stm32l4x5_usart_base_write()
503 s->isr &= ~value; in stm32l4x5_usart_base_write()
511 s->tdr = value; in stm32l4x5_usart_base_write()
512 s->isr &= ~R_ISR_TXE_MASK; in stm32l4x5_usart_base_write()
546 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); in stm32l4x5_usart_base_init()
548 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, in stm32l4x5_usart_base_init()
550 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); in stm32l4x5_usart_base_init()
552 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); in stm32l4x5_usart_base_init()
588 if (!clock_has_source(s->clk)) { in stm32l4x5_usart_base_realize()
593 qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, in stm32l4x5_usart_base_realize()
603 rc->phases.hold = stm32l4x5_usart_base_reset_hold; in stm32l4x5_usart_base_class_init()
605 dc->realize = stm32l4x5_usart_base_realize; in stm32l4x5_usart_base_class_init()
606 dc->vmsd = &vmstate_stm32l4x5_usart_base; in stm32l4x5_usart_base_class_init()
613 subc->type = STM32L4x5_USART; in stm32l4x5_usart_class_init()
620 subc->type = STM32L4x5_UART; in stm32l4x5_uart_class_init()
627 subc->type = STM32L4x5_LPUART; in stm32l4x5_lpuart_class_init()