111     if (!fifo8_is_full(&s->recv_fifo)) {  in recv_fifo_put()
112         fifo8_push(&s->recv_fifo, chr);  in recv_fifo_put()
131                 s->recv_fifo.num >= s->recv_fifo_itl)) {  in serial_update_irq()
419             fifo8_reset(&s->recv_fifo);  in serial_ioport_write()
482                 ret = fifo8_is_empty(&s->recv_fifo) ?  in serial_ioport_read()
483                             0 : fifo8_pop(&s->recv_fifo);  in serial_ioport_read()
484                 if (s->recv_fifo.num == 0) {  in serial_ioport_read()
558         if (s->recv_fifo.num < UART_FIFO_LENGTH) {  in serial_can_receive()
566             return (s->recv_fifo.num <= s->recv_fifo_itl) ?  in serial_can_receive()
567                         s->recv_fifo_itl - s->recv_fifo.num : 1;  in serial_can_receive()
588     if (s->recv_fifo.num) {  in fifo_timeout_int()
738     return !fifo8_is_empty(&s->recv_fifo);  in serial_recv_fifo_needed()
748         VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
881     fifo8_reset(&s->recv_fifo);  in serial_reset()
933     fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);  in serial_realize()
948     fifo8_destroy(&s->recv_fifo);  in serial_unrealize()