hw/char/max78000_uart.c

22     Max78000UartState *s = opaque;
23     if (!(s->ctrl & UART_BCLKEN)) {
26     return fifo8_num_free(&s->rx_fifo);
29 static void max78000_update_irq(Max78000UartState *s)
33     interrupt_level = s->int_fl & s->int_en;
34     qemu_set_irq(s->irq, interrupt_level);
39     Max78000UartState *s = opaque;
41     assert(size <= fifo8_num_free(&s->rx_fifo));
43     fifo8_push_all(&s->rx_fifo, buf, size);
45     uint32_t rx_threshold = s->ctrl & 0xf;
47     if (fifo8_num_used(&s->rx_fifo) >= rx_threshold) {
48         s->int_fl |= UART_RX_THD;
51     max78000_update_irq(s);
56     Max78000UartState *s = MAX78000_UART(obj);
58     s->ctrl = 0;
59     s->status = UART_TX_EM | UART_RX_EM;
60     s->int_en = 0;
61     s->int_fl = 0;
62     s->osr = 0;
63     s->txpeek = 0;
64     s->pnr = UART_RTS;
65     s->fifo = 0;
66     s->dma = 0;
67     s->wken = 0;
68     s->wkfl = 0;
69     fifo8_reset(&s->rx_fifo);
75     Max78000UartState *s = opaque;
79         retvalue = s->ctrl;
82         retvalue = (fifo8_num_used(&s->rx_fifo) << UART_RX_LVL) |
84                     (fifo8_is_empty(&s->rx_fifo) ? UART_RX_EM : 0);
87         retvalue = s->int_en;
90         retvalue = s->int_fl;
93         retvalue = s->clkdiv;
96         retvalue = s->osr;
99         if (!fifo8_is_empty(&s->rx_fifo)) {
100             retvalue = fifo8_peek(&s->rx_fifo);
104         retvalue = s->pnr;
107         if (!fifo8_is_empty(&s->rx_fifo)) {
108             retvalue = fifo8_pop(&s->rx_fifo);
109             max78000_update_irq(s);
114         retvalue = s->dma;
117         retvalue = s->wken;
120         retvalue = s->wkfl;
124             "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
134     Max78000UartState *s = opaque;
142             fifo8_reset(&s->rx_fifo);
147         s->ctrl = value & ~(UART_FLUSH_RX | UART_FLUSH_TX);
160         s->int_en = value;
163         s->int_fl = s->int_fl & ~(value);
164         max78000_update_irq(s);
167         s->clkdiv = value;
170         s->osr = value;
173         s->pnr = value;
181         qemu_chr_fe_write_all(&s->chr, &data, 1);
184         s->int_fl |= UART_TX_HE;
185         max78000_update_irq(s);
190         s->dma = value;
193         s->wken = value;
196         s->wkfl = value;
199         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
240     Max78000UartState *s = MAX78000_UART(obj);
241     fifo8_create(&s->rx_fifo, 8);
243     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
245     memory_region_init_io(&s->mmio, obj, &max78000_uart_ops, s,
247     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
252     Max78000UartState *s = MAX78000_UART(obj);
253     fifo8_destroy(&s->rx_fifo);
258     Max78000UartState *s = MAX78000_UART(dev);
260     qemu_chr_fe_set_handlers(&s->chr, max78000_uart_can_receive,
262                              s, NULL, true);