Lines Matching +full:imx31 +full:- +full:uart
2 * IMX31 UARTS
7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
10 * See the COPYING file in the top-level directory.
12 * This is a `bare-bones' implementation of the IMX series serial ports.
14 * -- implement FIFOs. The real hardware has 32 word transmit
15 * and receive FIFOs; we currently use a 1-char buffer
16 * -- implement DMA
17 * -- implement BAUD-rate and modem lines, for when the backend
24 #include "hw/qdev-properties.h"
25 #include "hw/qdev-properties-system.h"
75 usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); in imx_update()
79 usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; in imx_update()
84 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; in imx_update()
90 mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN); in imx_update()
92 usr2 = s->usr2 & mask; in imx_update()
94 qemu_set_irq(s->irq, usr1 || usr2); in imx_update()
100 if (fifo32_is_full(&s->rx_fifo)) { in imx_serial_rx_fifo_push()
102 s->usr2 |= USR2_ORE; in imx_serial_rx_fifo_push()
104 if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) { in imx_serial_rx_fifo_push()
108 fifo32_push(&s->rx_fifo, pushed_value); in imx_serial_rx_fifo_push()
114 if (fifo32_is_empty(&s->rx_fifo)) { in imx_serial_rx_fifo_pop()
117 return fifo32_pop(&s->rx_fifo); in imx_serial_rx_fifo_pop()
123 s->usr1 |= USR1_AGTIM; in imx_serial_rx_fifo_ageing_timer_int()
139 if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) { in imx_serial_rx_fifo_ageing_timer_restart()
140 timer_mod_ns(&s->ageing_timer, in imx_serial_rx_fifo_ageing_timer_restart()
143 timer_del(&s->ageing_timer); in imx_serial_rx_fifo_ageing_timer_restart()
150 s->usr1 = USR1_TRDY | USR1_RXDS; in imx_serial_reset()
154 s->usr1 |= USR1_RTSS; in imx_serial_reset()
155 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; in imx_serial_reset()
156 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; in imx_serial_reset()
157 s->ucr1 = 0; in imx_serial_reset()
158 s->ucr2 = UCR2_SRST; in imx_serial_reset()
159 s->ucr3 = 0x700; in imx_serial_reset()
160 s->ubmr = 0; in imx_serial_reset()
161 s->ubrc = 4; in imx_serial_reset()
163 fifo32_reset(&s->rx_fifo); in imx_serial_reset()
164 timer_del(&s->ageing_timer); in imx_serial_reset()
174 * enable the uart on boot, so messages from the linux decompressor in imx_serial_reset_at_boot()
178 s->ucr1 = UCR1_UARTEN; in imx_serial_reset_at_boot()
179 s->ucr2 = UCR2_TXEN; in imx_serial_reset_at_boot()
188 uint8_t rxtl = s->ufcr & TL_MASK; in imx_serial_read()
195 if (!(s->uts1 & UTS1_RXEMPTY)) { in imx_serial_read()
198 rx_used = fifo32_num_used(&s->rx_fifo); in imx_serial_read()
201 s->usr1 &= ~USR1_RRDY; in imx_serial_read()
204 s->usr2 &= ~USR2_RDR; in imx_serial_read()
205 s->uts1 |= UTS1_RXEMPTY; in imx_serial_read()
209 qemu_chr_fe_accept_input(&s->chr); in imx_serial_read()
214 return s->ucr1; in imx_serial_read()
217 return s->ucr2; in imx_serial_read()
220 return s->usr1; in imx_serial_read()
223 return s->usr2; in imx_serial_read()
226 return s->ubmr; in imx_serial_read()
229 return s->ubrc; in imx_serial_read()
232 return s->uts1; in imx_serial_read()
235 return s->ufcr; in imx_serial_read()
238 return s->onems; in imx_serial_read()
241 return s->ucr3; in imx_serial_read()
244 return s->ucr4; in imx_serial_read()
260 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); in imx_serial_write()
264 offset, (unsigned int)value, chr ? chr->label : "NODEV"); in imx_serial_write()
269 if (s->ucr2 & UCR2_TXEN) { in imx_serial_write()
272 qemu_chr_fe_write_all(&s->chr, &ch, 1); in imx_serial_write()
273 s->usr1 &= ~USR1_TRDY; in imx_serial_write()
274 s->usr2 &= ~USR2_TXDC; in imx_serial_write()
276 s->usr1 |= USR1_TRDY; in imx_serial_write()
277 s->usr2 |= USR2_TXDC; in imx_serial_write()
283 s->ucr1 = value & 0xffff; in imx_serial_write()
293 * If it's intended to use a real serial device as a back-end, this in imx_serial_write()
302 if (!(s->ucr2 & UCR2_RXEN)) { in imx_serial_write()
303 qemu_chr_fe_accept_input(&s->chr); in imx_serial_write()
306 s->ucr2 = value & 0xffff; in imx_serial_write()
312 s->usr1 &= ~value; in imx_serial_write()
323 s->usr2 &= ~value; in imx_serial_write()
331 s->ubrc = value & 0xffff; in imx_serial_write()
335 s->ubmr = value & 0xffff; in imx_serial_write()
339 s->onems = value & 0xffff; in imx_serial_write()
343 s->ufcr = value & 0xffff; in imx_serial_write()
347 s->ucr3 = value & 0xffff; in imx_serial_write()
351 s->ucr4 = value & 0xffff; in imx_serial_write()
370 return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; in imx_can_receive()
376 uint8_t rxtl = s->ufcr & TL_MASK; in imx_put_data()
380 if (fifo32_num_used(&s->rx_fifo) >= rxtl) { in imx_put_data()
381 s->usr1 |= USR1_RRDY; in imx_put_data()
386 s->usr2 |= USR2_RDR; in imx_put_data()
387 s->uts1 &= ~UTS1_RXEMPTY; in imx_put_data()
389 s->usr2 |= USR2_BRCD; in imx_put_data()
398 s->usr2 |= USR2_WAKE; in imx_receive()
420 fifo32_create(&s->rx_fifo, FIFO_SIZE); in imx_serial_realize()
421 timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, in imx_serial_realize()
424 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); in imx_serial_realize()
426 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, in imx_serial_realize()
435 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, in imx_serial_init()
437 sysbus_init_mmio(sbd, &s->iomem); in imx_serial_init()
438 sysbus_init_irq(sbd, &s->irq); in imx_serial_init()
450 dc->realize = imx_serial_realize; in imx_serial_class_init()
451 dc->vmsd = &vmstate_imx_serial; in imx_serial_class_init()
453 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); in imx_serial_class_init()
454 dc->desc = "i.MX series UART"; in imx_serial_class_init()