Lines Matching refs:uart_intr_state
79 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { in ibex_uart_update_irqs()
85 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { in ibex_uart_update_irqs()
91 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) { in ibex_uart_update_irqs()
97 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) { in ibex_uart_update_irqs()
133 s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; in ibex_uart_receive()
156 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; in ibex_uart_xmit()
157 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; in ibex_uart_xmit()
185 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; in ibex_uart_xmit()
191 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; in ibex_uart_xmit()
218 s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK; in uart_write_tx_fifo()
234 s->uart_intr_state = 0x00000000; in ibex_uart_reset()
235 s->uart_intr_state = 0x00000000; in ibex_uart_reset()
273 retvalue = s->uart_intr_state; in ibex_uart_read()
354 s->uart_intr_state &= ~value; in ibex_uart_write()
362 s->uart_intr_state |= value; in ibex_uart_write()
497 VMSTATE_UINT32(uart_intr_state, IbexUartState),