49 #define UTRSTAT    0x0010 /* Tx/Rx Status             */  macro
80     {"UTRSTAT",  UTRSTAT,  0x00000006}, /* RO */
310     } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {  in exynos4210_uart_update_irq()
330     trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)],  in exynos4210_uart_timeout_int()
333     if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) ||  in exynos4210_uart_timeout_int()
336         s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;  in exynos4210_uart_timeout_int()
432             s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |  in exynos4210_uart_write()
439             s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |  in exynos4210_uart_write()
452     case UTRSTAT:  in exynos4210_uart_write()
454             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT;  in exynos4210_uart_write()
508                     s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;  in exynos4210_uart_read()
510                     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;  in exynos4210_uart_read()
519             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;  in exynos4210_uart_read()
560         return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY);  in exynos4210_uart_can_receive()
581     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;  in exynos4210_uart_receive()