258     if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) ||  in escc_update_irq_chn()
260         ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||  in escc_update_irq_chn()
261         ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&  in escc_update_irq_chn()
264         ((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&  in escc_update_irq_chn()
297     s->wregs[W_CMD] = 0;  in escc_soft_reset_chn()
298     s->wregs[W_INTR] &= INTR_PAR_SPEC | INTR_WTRQ_TXRX;  in escc_soft_reset_chn()
299     s->wregs[W_RXCTRL] &= ~RXCTRL_RXEN;  in escc_soft_reset_chn()
301     s->wregs[W_TXCTRL1] |= TXCTRL1_1STOP;  in escc_soft_reset_chn()
302     s->wregs[W_TXCTRL2] &= TXCTRL2_TXCRC | TXCTRL2_8BITS;  in escc_soft_reset_chn()
303     s->wregs[W_MINTR] &= ~MINTR_SOFTIACK;  in escc_soft_reset_chn()
304     s->wregs[W_MISC1] &= MISC1_ENC_MASK;  in escc_soft_reset_chn()
306     s->wregs[W_MISC2] &= MISC2_BRG_EN | MISC2_BRG_SRC |  in escc_soft_reset_chn()
308     s->wregs[W_MISC2] |= MISC2_PLLCMD0;  in escc_soft_reset_chn()
310     s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |  in escc_soft_reset_chn()
333     s->wregs[W_MINTR] &= MINTR_VIS | MINTR_NV;  in escc_hard_reset_chn()
334     s->wregs[W_MINTR] |= MINTR_RST_B | MINTR_RST_A;  in escc_hard_reset_chn()
335     s->wregs[W_MISC1] = 0;  in escc_hard_reset_chn()
336     s->wregs[W_CLOCK] = CLOCK_TRXC;  in escc_hard_reset_chn()
337     s->wregs[W_MISC2] &= MISC2_PLLCMD1 | MISC2_PLLCMD2;  in escc_hard_reset_chn()
338     s->wregs[W_MISC2] |= MISC2_LCL_LOOP | MISC2_PLLCMD0;  in escc_hard_reset_chn()
358             cs->wregs[j] = 0;  in escc_reset()
385         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in set_rxint()
392         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in set_rxint()
407             if (s->wregs[W_INTR] & INTR_TXINT) {  in set_txint()
410             if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in set_txint()
417             if (s->wregs[W_INTR] & INTR_TXINT) {  in set_txint()
430         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in clr_rxint()
437         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in clr_rxint()
455         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in clr_txint()
463         if (s->wregs[W_MINTR] & MINTR_STATUSHI) {  in clr_txint()
485     if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {  in escc_update_parameters()
486         if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) {  in escc_update_parameters()
494     if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) {  in escc_update_parameters()
499     switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {  in escc_update_parameters()
514     speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);  in escc_update_parameters()
515     switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {  in escc_update_parameters()
580             s->wregs[s->reg] = val;  in escc_mem_write()
589             s->wregs[s->reg] = val;  in escc_mem_write()
592             s->wregs[s->reg] = val;  in escc_mem_write()
607             s->wregs[s->reg] = val;  in escc_mem_write()
612             s->wregs[s->reg] = val;  in escc_mem_write()
655         if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */  in escc_mem_write()
656             if (s->wregs[W_MISC2] & MISC2_LCL_LOOP) {  in escc_mem_write()
727     if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) /* Rx not enabled */  in serial_can_receive()
778         VMSTATE_BUFFER(wregs, ESCCChannelState),