Lines Matching +full:- +full:chn +full:- +full:disabled
4 * Copyright (c) 2003-2005 Fabrice Bellard
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
45 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
70 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
74 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
77 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
202 return s->bit_swap ? s->it_shift + 1 : s->it_shift; in reg_shift()
207 return s->bit_swap ? s->it_shift : s->it_shift + 1; in chn_shift()
213 ESCCSERIOQueue *q = &s->queue; in clear_queue()
214 q->rptr = q->wptr = q->count = 0; in clear_queue()
220 ESCCSERIOQueue *q = &s->queue; in put_queue()
223 if (q->count >= ESCC_SERIO_QUEUE_SIZE) { in put_queue()
226 q->data[q->wptr] = b; in put_queue()
227 if (++q->wptr == ESCC_SERIO_QUEUE_SIZE) { in put_queue()
228 q->wptr = 0; in put_queue()
230 q->count++; in put_queue()
237 ESCCSERIOQueue *q = &s->queue; in get_queue()
240 if (q->count == 0) { in get_queue()
243 val = q->data[q->rptr]; in get_queue()
244 if (++q->rptr == ESCC_SERIO_QUEUE_SIZE) { in get_queue()
245 q->rptr = 0; in get_queue()
247 q->count--; in get_queue()
250 if (q->count > 0) { in get_queue()
258 if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || in escc_update_irq_chn()
260 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || in escc_update_irq_chn()
261 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && in escc_update_irq_chn()
262 s->rxint == 1) || in escc_update_irq_chn()
264 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && in escc_update_irq_chn()
265 (s->rregs[R_STATUS] & STATUS_BRK)))) { in escc_update_irq_chn()
277 irq |= escc_update_irq_chn(s->otherchn); in escc_update_irq()
280 qemu_set_irq(s->irq, irq); in escc_update_irq()
285 s->reg = 0; in escc_reset_chn()
286 s->rx = s->tx = 0; in escc_reset_chn()
287 s->rxint = s->txint = 0; in escc_reset_chn()
288 s->rxint_under_svc = s->txint_under_svc = 0; in escc_reset_chn()
289 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; in escc_reset_chn()
290 s->sunmouse_dx = s->sunmouse_dy = s->sunmouse_buttons = 0; in escc_reset_chn()
298 s->wregs[W_CMD] = 0; in escc_soft_reset_chn()
299 s->wregs[W_INTR] &= INTR_PAR_SPEC | INTR_WTRQ_TXRX; in escc_soft_reset_chn()
300 s->wregs[W_RXCTRL] &= ~RXCTRL_RXEN; in escc_soft_reset_chn()
302 s->wregs[W_TXCTRL1] |= TXCTRL1_1STOP; in escc_soft_reset_chn()
303 s->wregs[W_TXCTRL2] &= TXCTRL2_TXCRC | TXCTRL2_8BITS; in escc_soft_reset_chn()
304 s->wregs[W_MINTR] &= ~MINTR_SOFTIACK; in escc_soft_reset_chn()
305 s->wregs[W_MISC1] &= MISC1_ENC_MASK; in escc_soft_reset_chn()
306 /* PLL disabled */ in escc_soft_reset_chn()
307 s->wregs[W_MISC2] &= MISC2_BRG_EN | MISC2_BRG_SRC | in escc_soft_reset_chn()
309 s->wregs[W_MISC2] |= MISC2_PLLCMD0; in escc_soft_reset_chn()
311 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | in escc_soft_reset_chn()
314 s->rregs[R_STATUS] &= STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS_BRK; in escc_soft_reset_chn()
315 s->rregs[R_STATUS] |= STATUS_TXEMPTY | STATUS_TXUNDRN; in escc_soft_reset_chn()
316 if (s->disabled) { in escc_soft_reset_chn()
317 s->rregs[R_STATUS] |= STATUS_DCD | STATUS_SYNC | STATUS_CTS; in escc_soft_reset_chn()
319 s->rregs[R_SPEC] &= SPEC_ALLSENT; in escc_soft_reset_chn()
320 s->rregs[R_SPEC] |= SPEC_BITS8; in escc_soft_reset_chn()
321 s->rregs[R_INTR] = 0; in escc_soft_reset_chn()
322 s->rregs[R_MISC] &= MISC_2CLKMISS; in escc_soft_reset_chn()
334 s->wregs[W_MINTR] &= MINTR_VIS | MINTR_NV; in escc_hard_reset_chn()
335 s->wregs[W_MINTR] |= MINTR_RST_B | MINTR_RST_A; in escc_hard_reset_chn()
336 s->wregs[W_MISC1] = 0; in escc_hard_reset_chn()
337 s->wregs[W_CLOCK] = CLOCK_TRXC; in escc_hard_reset_chn()
338 s->wregs[W_MISC2] &= MISC2_PLLCMD1 | MISC2_PLLCMD2; in escc_hard_reset_chn()
339 s->wregs[W_MISC2] |= MISC2_LCL_LOOP | MISC2_PLLCMD0; in escc_hard_reset_chn()
348 ESCCChannelState *cs = &s->chn[i]; in escc_reset()
353 * power-on until an explicit hardware or software reset has been in escc_reset()
358 cs->rregs[j] = 0; in escc_reset()
359 cs->wregs[j] = 0; in escc_reset()
370 cs->rregs[R_STATUS] |= STATUS_TXEMPTY; in escc_reset()
378 s->rxint = 1; in set_rxint()
383 s->rxint_under_svc = 1; in set_rxint()
384 if (s->chn == escc_chn_a) { in set_rxint()
385 s->rregs[R_INTR] |= INTR_RXINTA; in set_rxint()
386 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in set_rxint()
387 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; in set_rxint()
389 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; in set_rxint()
392 s->otherchn->rregs[R_INTR] |= INTR_RXINTB; in set_rxint()
393 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in set_rxint()
394 s->rregs[R_IVEC] = IVEC_HIRXINTB; in set_rxint()
396 s->rregs[R_IVEC] = IVEC_LORXINTB; in set_rxint()
404 s->txint = 1; in set_txint()
405 if (!s->rxint_under_svc) { in set_txint()
406 s->txint_under_svc = 1; in set_txint()
407 if (s->chn == escc_chn_a) { in set_txint()
408 if (s->wregs[W_INTR] & INTR_TXINT) { in set_txint()
409 s->rregs[R_INTR] |= INTR_TXINTA; in set_txint()
411 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in set_txint()
412 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; in set_txint()
414 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; in set_txint()
417 s->rregs[R_IVEC] = IVEC_TXINTB; in set_txint()
418 if (s->wregs[W_INTR] & INTR_TXINT) { in set_txint()
419 s->otherchn->rregs[R_INTR] |= INTR_TXINTB; in set_txint()
428 s->rxint = 0; in clr_rxint()
429 s->rxint_under_svc = 0; in clr_rxint()
430 if (s->chn == escc_chn_a) { in clr_rxint()
431 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in clr_rxint()
432 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; in clr_rxint()
434 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; in clr_rxint()
436 s->rregs[R_INTR] &= ~INTR_RXINTA; in clr_rxint()
438 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in clr_rxint()
439 s->rregs[R_IVEC] = IVEC_HINOINT; in clr_rxint()
441 s->rregs[R_IVEC] = IVEC_LONOINT; in clr_rxint()
443 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; in clr_rxint()
445 if (s->txint) { in clr_rxint()
453 s->txint = 0; in clr_txint()
454 s->txint_under_svc = 0; in clr_txint()
455 if (s->chn == escc_chn_a) { in clr_txint()
456 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in clr_txint()
457 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; in clr_txint()
459 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; in clr_txint()
461 s->rregs[R_INTR] &= ~INTR_TXINTA; in clr_txint()
463 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; in clr_txint()
464 if (s->wregs[W_MINTR] & MINTR_STATUSHI) { in clr_txint()
465 s->rregs[R_IVEC] = IVEC_HINOINT; in clr_txint()
467 s->rregs[R_IVEC] = IVEC_LONOINT; in clr_txint()
469 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; in clr_txint()
471 if (s->rxint) { in clr_txint()
482 if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != escc_serial) { in escc_update_parameters()
486 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { in escc_update_parameters()
487 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) { in escc_update_parameters()
495 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) { in escc_update_parameters()
500 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { in escc_update_parameters()
515 speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); in escc_update_parameters()
516 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { in escc_update_parameters()
535 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in escc_update_parameters()
549 s = &serial->chn[channel]; in escc_mem_write()
552 trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); in escc_mem_write()
554 switch (s->reg) { in escc_mem_write()
566 if (s->rxint_under_svc) { in escc_mem_write()
567 s->rxint_under_svc = 0; in escc_mem_write()
568 if (s->txint) { in escc_mem_write()
571 } else if (s->txint_under_svc) { in escc_mem_write()
572 s->txint_under_svc = 0; in escc_mem_write()
581 s->wregs[s->reg] = val; in escc_mem_write()
583 s->rregs[R_STATUS] |= STATUS_SYNC; in escc_mem_write()
590 s->wregs[s->reg] = val; in escc_mem_write()
593 s->wregs[s->reg] = val; in escc_mem_write()
604 s->rregs[R_SPEC] |= SPEC_ALLSENT; in escc_mem_write()
608 s->wregs[s->reg] = val; in escc_mem_write()
613 s->wregs[s->reg] = val; in escc_mem_write()
614 s->rregs[s->reg] = val; in escc_mem_write()
623 trace_escc_soft_reset_chn(CHN_C(&serial->chn[0])); in escc_mem_write()
624 escc_soft_reset_chn(&serial->chn[0]); in escc_mem_write()
627 trace_escc_soft_reset_chn(CHN_C(&serial->chn[1])); in escc_mem_write()
628 escc_soft_reset_chn(&serial->chn[1]); in escc_mem_write()
632 escc_hard_reset_chn(&serial->chn[0]); in escc_mem_write()
633 escc_hard_reset_chn(&serial->chn[1]); in escc_mem_write()
640 if (s->reg == 0) { in escc_mem_write()
641 s->reg = newreg; in escc_mem_write()
643 s->reg = 0; in escc_mem_write()
653 s->txint = 0; in escc_mem_write()
655 s->tx = val; in escc_mem_write()
656 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */ in escc_mem_write()
657 if (s->wregs[W_MISC2] & MISC2_LCL_LOOP) { in escc_mem_write()
658 serial_receive_byte(s, s->tx); in escc_mem_write()
659 } else if (qemu_chr_fe_backend_connected(&s->chr)) { in escc_mem_write()
664 qemu_chr_fe_write_all(&s->chr, &s->tx, 1); in escc_mem_write()
665 } else if (s->type == escc_kbd && !s->disabled) { in escc_mem_write()
669 s->rregs[R_STATUS] |= STATUS_TXEMPTY; /* Tx buffer empty */ in escc_mem_write()
670 s->rregs[R_SPEC] |= SPEC_ALLSENT; /* All sent */ in escc_mem_write()
689 s = &serial->chn[channel]; in escc_mem_read()
692 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); in escc_mem_read()
693 ret = s->rregs[s->reg]; in escc_mem_read()
694 s->reg = 0; in escc_mem_read()
697 s->rregs[R_STATUS] &= ~STATUS_RXAV; in escc_mem_read()
699 if (s->type == escc_kbd || s->type == escc_mouse) { in escc_mem_read()
702 ret = s->rx; in escc_mem_read()
705 qemu_chr_fe_accept_input(&s->chr); in escc_mem_read()
728 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) /* Rx not enabled */ in serial_can_receive()
729 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) { in serial_can_receive()
741 s->rregs[R_STATUS] |= STATUS_RXAV; in serial_receive_byte()
742 s->rx = ch; in serial_receive_byte()
748 s->rregs[R_STATUS] |= STATUS_BRK; in serial_receive_break()
790 VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn,
803 assert(evt->type == INPUT_EVENT_KIND_KEY); in sunkbd_handle_event()
804 key = evt->u.key.data; in sunkbd_handle_event()
805 qcode = qemu_input_key_value_to_qcode(key->key); in sunkbd_handle_event()
807 key->down); in sunkbd_handle_event()
810 if (key->down) { in sunkbd_handle_event()
811 s->caps_lock_mode ^= 1; in sunkbd_handle_event()
812 if (s->caps_lock_mode == 2) { in sunkbd_handle_event()
816 s->caps_lock_mode ^= 2; in sunkbd_handle_event()
817 if (s->caps_lock_mode == 3) { in sunkbd_handle_event()
824 if (key->down) { in sunkbd_handle_event()
825 s->num_lock_mode ^= 1; in sunkbd_handle_event()
826 if (s->num_lock_mode == 2) { in sunkbd_handle_event()
830 s->num_lock_mode ^= 2; in sunkbd_handle_event()
831 if (s->num_lock_mode == 3) { in sunkbd_handle_event()
842 if (!key->down) { in sunkbd_handle_event()
857 /* Return the value of the dip-switches in a SUN Type 5 keyboard */ in sunkbd_layout_dip_switch()
867 * Dip values from table 3-16 Layouts for Type 4, 5 and 5c Keyboards in sunkbd_layout_dip_switch()
870 {"en-us", 0x21}, /* U.S.A. (US5.kt) */ in sunkbd_layout_dip_switch()
881 {"fr-ch", 0x2c}, /* Switzerland/French (Switzer_Fr5.kt) */ in sunkbd_layout_dip_switch()
882 {"de-ch", 0x2d}, /* Switzerland/German (Switzer_Ge5.kt) */ in sunkbd_layout_dip_switch()
883 {"en-gb", 0x2e}, /* Great Britain (UK5.kt) */ in sunkbd_layout_dip_switch()
887 {"fr-ca", 0x32}, /* Canada/French (Canada_Fr5.kt) */ in sunkbd_layout_dip_switch()
893 {"tr", 0x38}, /* Turkey-Q5 (TurkeyQ5.kt) */ in sunkbd_layout_dip_switch()
897 {"nl-be", 0x3c}, /* Belgium (Belgian5.kt) */ in sunkbd_layout_dip_switch()
923 ret = 0x21; /* en-us layout */ in sunkbd_layout_dip_switch()
931 if (s->led_mode) { /* Ignore led byte */ in handle_kbd_command()
932 s->led_mode = 0; in handle_kbd_command()
943 s->led_mode = 1; in handle_kbd_command()
949 put_queue(s, sunkbd_layout_dip_switch(s->sunkbd_layout)); in handle_kbd_command()
968 switch (evt->type) { in sunmouse_handle_event()
970 move = evt->u.rel.data; in sunmouse_handle_event()
971 if (move->axis == INPUT_AXIS_X) { in sunmouse_handle_event()
972 s->sunmouse_dx += move->value; in sunmouse_handle_event()
973 } else if (move->axis == INPUT_AXIS_Y) { in sunmouse_handle_event()
974 s->sunmouse_dy -= move->value; in sunmouse_handle_event()
979 btn = evt->u.btn.data; in sunmouse_handle_event()
980 if (bmap[btn->button]) { in sunmouse_handle_event()
981 if (btn->down) { in sunmouse_handle_event()
982 s->sunmouse_buttons |= bmap[btn->button]; in sunmouse_handle_event()
984 s->sunmouse_buttons &= ~bmap[btn->button]; in sunmouse_handle_event()
987 s->sunmouse_buttons |= 0x80; in sunmouse_handle_event()
1002 if (s->sunmouse_dx == 0 && s->sunmouse_dy == 0 && in sunmouse_sync()
1003 (s->sunmouse_buttons & 0x80) == 0) { in sunmouse_sync()
1009 s->sunmouse_buttons &= ~0x80; in sunmouse_sync()
1010 trace_escc_sunmouse_event(s->sunmouse_dx, s->sunmouse_dy, in sunmouse_sync()
1011 s->sunmouse_buttons); in sunmouse_sync()
1013 ch ^= s->sunmouse_buttons; in sunmouse_sync()
1016 ch = s->sunmouse_dx; in sunmouse_sync()
1019 } else if (ch < -127) { in sunmouse_sync()
1020 ch = -127; in sunmouse_sync()
1023 s->sunmouse_dx -= ch; in sunmouse_sync()
1025 ch = s->sunmouse_dy; in sunmouse_sync()
1028 } else if (ch < -127) { in sunmouse_sync()
1029 ch = -127; in sunmouse_sync()
1032 s->sunmouse_dy -= ch; in sunmouse_sync()
1053 sysbus_init_irq(dev, &s->chn[i].irq); in escc_init1()
1054 s->chn[i].chn = 1 - i; in escc_init1()
1056 s->chn[0].otherchn = &s->chn[1]; in escc_init1()
1057 s->chn[1].otherchn = &s->chn[0]; in escc_init1()
1059 sysbus_init_mmio(dev, &s->mmio); in escc_init1()
1067 s->chn[0].disabled = s->disabled; in escc_realize()
1068 s->chn[1].disabled = s->disabled; in escc_realize()
1070 memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc", in escc_realize()
1071 ESCC_SIZE << s->it_shift); in escc_realize()
1074 if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) { in escc_realize()
1075 s->chn[i].clock = s->frequency / 2; in escc_realize()
1076 qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive, in escc_realize()
1078 &s->chn[i], NULL, true); in escc_realize()
1082 if (s->chn[0].type == escc_mouse) { in escc_realize()
1083 s->chn[0].hs = qemu_input_handler_register((DeviceState *)(&s->chn[0]), in escc_realize()
1086 if (s->chn[1].type == escc_kbd) { in escc_realize()
1087 s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]), in escc_realize()
1096 DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
1097 DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
1098 DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
1099 DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr),
1100 DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr),
1101 DEFINE_PROP_STRING("chnA-sunkbd-layout", ESCCState, chn[1].sunkbd_layout),
1110 dc->realize = escc_realize; in escc_class_init()
1111 dc->vmsd = &vmstate_escc; in escc_class_init()
1113 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); in escc_class_init()