252     drive->swimctrl = bus->ctrl;  in swim_drive_realize()
283     SWIMCtrl *swimctrl = opaque;  in iwmctrl_write()  local
291         swimctrl->iwm_latches |= (1 << latch);  in iwmctrl_write()
293         swimctrl->iwm_latches &= ~(1 << latch);  in iwmctrl_write()
296     reg = (swimctrl->iwm_latches & 0xc0) >> 5 |  in iwmctrl_write()
297           (swimctrl->iwm_latches & 0x10) >> 4;  in iwmctrl_write()
299     swimctrl->iwmregs[reg] = value;  in iwmctrl_write()
307         switch (swimctrl->iwm_switch) {  in iwmctrl_write()
310                 swimctrl->iwm_switch++;  in iwmctrl_write()
315                 swimctrl->iwm_switch++;  in iwmctrl_write()
320                 swimctrl->iwm_switch++;  in iwmctrl_write()
325                 swimctrl->iwm_switch++;  in iwmctrl_write()
327                 swimctrl->mode = SWIM_MODE_ISM;  in iwmctrl_write()
328                 swimctrl->swim_mode |= (1 << SWIM_MODE_STATUS_BIT);  in iwmctrl_write()
329                 swimctrl->iwm_switch = 0;  in iwmctrl_write()
333                 memory_region_del_subregion(&swimctrl->swim, &swimctrl->iwm);  in iwmctrl_write()
334                 memory_region_add_subregion(&swimctrl->swim, 0x0,  in iwmctrl_write()
335                                             &swimctrl->ism);  in iwmctrl_write()
347     SWIMCtrl *swimctrl = opaque;  in iwmctrl_read()  local
355         swimctrl->iwm_latches |= (1 << latch);  in iwmctrl_read()
357         swimctrl->iwm_latches &= ~(1 << latch);  in iwmctrl_read()
360     reg = (swimctrl->iwm_latches & 0xc0) >> 5 |  in iwmctrl_read()
361           (swimctrl->iwm_latches & 0x10) >> 4;  in iwmctrl_read()
385     SWIMCtrl *swimctrl = opaque;  in ismctrl_write()  local
393         swimctrl->swim_phase = value;  in ismctrl_write()
396         swimctrl->swim_mode &= ~value;  in ismctrl_write()
398         swimctrl->pram_idx = 0;  in ismctrl_write()
400         if (!(swimctrl->swim_mode & (1 << SWIM_MODE_STATUS_BIT))) {  in ismctrl_write()
402             swimctrl->mode = SWIM_MODE_IWM;  in ismctrl_write()
403             swimctrl->iwm_latches = 0;  in ismctrl_write()
407             memory_region_del_subregion(&swimctrl->swim, &swimctrl->ism);  in ismctrl_write()
408             memory_region_add_subregion(&swimctrl->swim, 0x0,  in ismctrl_write()
409                                         &swimctrl->iwm);  in ismctrl_write()
413         swimctrl->swim_mode |= value;  in ismctrl_write()
416         swimctrl->pram[swimctrl->pram_idx++] = value;  in ismctrl_write()
417         swimctrl->pram_idx &= 0xf;  in ismctrl_write()
429     SWIMCtrl *swimctrl = opaque;  in ismctrl_read()  local
436         value = swimctrl->swim_phase;  in ismctrl_read()
439         if (swimctrl->swim_phase == SWIM_DRIVE_PRESENT) {  in ismctrl_read()
445         value = swimctrl->pram[swimctrl->pram_idx++];  in ismctrl_read()
446         swimctrl->pram_idx &= 0xf;  in ismctrl_read()
449         value = swimctrl->swim_status & ~(1 << SWIM_MODE_STATUS_BIT);  in ismctrl_read()
450         if (swimctrl->swim_mode == SWIM_MODE_ISM) {  in ismctrl_read()
493     SWIMCtrl *swimctrl = &sbs->ctrl;  in sysbus_swim_init()  local
495     memory_region_init(&swimctrl->swim, obj, "swim", 0x2000);  in sysbus_swim_init()
496     memory_region_init_io(&swimctrl->iwm, obj, &swimctrl_iwm_ops, swimctrl,  in sysbus_swim_init()
498     memory_region_init_io(&swimctrl->ism, obj, &swimctrl_ism_ops, swimctrl,  in sysbus_swim_init()
500     sysbus_init_mmio(sbd, &swimctrl->swim);  in sysbus_swim_init()
506     SWIMCtrl *swimctrl = &sys->ctrl;  in sysbus_swim_realize()  local
508     qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);  in sysbus_swim_realize()
509     swimctrl->bus.ctrl = swimctrl;  in sysbus_swim_realize()
512     memory_region_add_subregion(&swimctrl->swim, 0x0, &swimctrl->iwm);  in sysbus_swim_realize()