Lines Matching +full:0 +full:- +full:64
26 #include "sysemu/block-backend.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
36 #include "qemu/error-report.h"
43 #define MAX_3BYTES_SIZE 0x1000000
46 /* Fields for FlashPartInfo->flags */
48 ER_4K = BIT(0),
67 * command (opcode 0xd8).
87 ((_jedec_id) >> 16) & 0xff,\
88 ((_jedec_id) >> 8) & 0xff,\
89 (_jedec_id) & 0xff,\
90 ((_ext_id) >> 8) & 0xff,\
91 (_ext_id) & 0xff,\
93 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
98 .die_cnt = 0
103 ((_jedec_id) >> 16) & 0xff,\
104 ((_jedec_id) >> 8) & 0xff,\
105 (_jedec_id) & 0xff,\
106 ((_ext_id) >> 16) & 0xff,\
107 ((_ext_id) >> 8) & 0xff,\
108 (_ext_id) & 0xff,\
115 .die_cnt = 0
121 ((_jedec_id) >> 16) & 0xff,\
122 ((_jedec_id) >> 8) & 0xff,\
123 (_jedec_id) & 0xff,\
124 ((_ext_id) >> 8) & 0xff,\
125 (_ext_id) & 0xff,\
127 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
134 #define JEDEC_NUMONYX 0x20
135 #define JEDEC_WINBOND 0xEF
136 #define JEDEC_SPANSION 0x01
139 #define VCFG_DUMMY 0x1
140 #define VCFG_WRAP_SEQUENTIAL 0x2
154 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
158 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
162 #define SPANSION_QUAD_CFG_POS 0
164 #define SPANSION_DUMMY_CLK_POS 0
178 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
179 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
180 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
182 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
183 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
184 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
186 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
187 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
188 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
189 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
191 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
194 * Atmel EEPROMS - it is assumed, that don't care bit in command
195 * is set to 0. Block protection is not supported.
197 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
198 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
200 /* EON -- en25xxx */
201 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
202 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
203 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
204 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
205 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
208 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
209 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
211 /* Intel/Numonyx -- xxxs33b */
212 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
213 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
214 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
215 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
218 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
219 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
220 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
221 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
225 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
226 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
227 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
228 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
232 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
233 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
234 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
235 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
236 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
237 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
238 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
239 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
240 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512,
242 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512,
244 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
245 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
246 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
247 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
248 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K),
252 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
253 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
254 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
255 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
256 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
257 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
258 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
259 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K),
261 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
262 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
263 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
264 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512,
267 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
268 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
269 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
270 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
273 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048,
276 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
277 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
278 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
279 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
280 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096,
282 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096,
286 * Spansion -- single (large) sector size only, at least
289 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
290 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
291 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
292 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
293 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
294 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
295 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
296 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
297 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
298 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
299 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
300 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
301 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
302 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
303 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
304 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
305 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
307 /* Spansion -- boot sectors support */
308 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
309 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
311 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
312 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
313 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
314 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
315 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
316 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
317 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
318 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
319 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
320 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
322 /* ST Microelectronics -- newer production may have feature updates */
323 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
324 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
325 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
326 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
327 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
328 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
329 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
330 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
331 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
332 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
334 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
335 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
336 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
338 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
339 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
340 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
342 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
343 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
344 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
345 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
347 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
348 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
349 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
350 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
351 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
352 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
353 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
354 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
355 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
356 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
357 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
358 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
359 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K),
361 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K),
363 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K),
365 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K),
369 { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) },
373 NOP = 0,
374 WRSR = 0x1,
375 WRDI = 0x4,
376 RDSR = 0x5,
377 WREN = 0x6,
378 BRRD = 0x16,
379 BRWR = 0x17,
380 JEDEC_READ = 0x9f,
381 BULK_ERASE_60 = 0x60,
382 BULK_ERASE = 0xc7,
383 READ_FSR = 0x70,
384 RDCR = 0x15,
385 RDSFDP = 0x5a,
387 READ = 0x03,
388 READ4 = 0x13,
389 FAST_READ = 0x0b,
390 FAST_READ4 = 0x0c,
391 DOR = 0x3b,
392 DOR4 = 0x3c,
393 QOR = 0x6b,
394 QOR4 = 0x6c,
395 DIOR = 0xbb,
396 DIOR4 = 0xbc,
397 QIOR = 0xeb,
398 QIOR4 = 0xec,
400 PP = 0x02,
401 PP4 = 0x12,
402 PP4_4 = 0x3e,
403 DPP = 0xa2,
404 QPP = 0x32,
405 QPP_4 = 0x34,
406 RDID_90 = 0x90,
407 RDID_AB = 0xab,
408 AAI_WP = 0xad,
410 ERASE_4K = 0x20,
411 ERASE4_4K = 0x21,
412 ERASE_32K = 0x52,
413 ERASE4_32K = 0x5c,
414 ERASE_SECTOR = 0xd8,
415 ERASE4_SECTOR = 0xdc,
417 EN_4BYTE_ADDR = 0xB7,
418 EX_4BYTE_ADDR = 0xE9,
420 EXTEND_ADDR_READ = 0xC8,
421 EXTEND_ADDR_WRITE = 0xC5,
423 RESET_ENABLE = 0x66,
424 RESET_MEMORY = 0x99,
427 * Micron: 0x35 - enable QPI
428 * Spansion: 0x35 - read control register
429 * Winbond: 0x35 - quad enable
431 RDCR_EQIO = 0x35,
432 RSTQIO = 0xf5,
435 * Winbond: 0x31 - write status register 2
437 WRSR2 = 0x31,
439 RNVCR = 0xB5,
440 WNVCR = 0xB1,
442 RVCR = 0x85,
443 WVCR = 0x81,
445 REVCR = 0x65,
446 WEVCR = 0x61,
448 DIE_ERASE = 0xC4,
472 MODE_STD = 0,
538 switch (s->pi->id[0]) { in OBJECT_DECLARE_TYPE()
539 case 0x20: in OBJECT_DECLARE_TYPE()
541 case 0xEF: in OBJECT_DECLARE_TYPE()
543 case 0x01: in OBJECT_DECLARE_TYPE()
545 case 0xC2: in OBJECT_DECLARE_TYPE()
547 case 0xBF: in OBJECT_DECLARE_TYPE()
549 case 0x9D: in OBJECT_DECLARE_TYPE()
573 if (!s->blk || !blk_is_writable(s->blk)) { in flash_sync_page()
579 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, in flash_sync_page()
580 s->pi->page_size); in flash_sync_page()
581 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, in flash_sync_page()
589 if (!s->blk || !blk_is_writable(s->blk)) { in flash_sync_area()
596 qemu_iovec_add(iov, s->storage + off, len); in flash_sync_area()
597 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); in flash_sync_area()
603 uint8_t capa_to_assert = 0; in flash_erase()
618 len = s->pi->sector_size; in flash_erase()
621 len = s->size; in flash_erase()
624 if (s->pi->die_cnt) { in flash_erase()
625 len = s->size / s->pi->die_cnt; in flash_erase()
626 offset = offset & (~(len - 1)); in flash_erase()
639 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { in flash_erase()
644 if (!s->write_enable) { in flash_erase()
648 memset(s->storage + offset, 0xff, len); in flash_erase()
654 if (s->dirty_page >= 0 && s->dirty_page != newpage) { in flash_sync_dirty()
655 flash_sync_page(s, s->dirty_page); in flash_sync_dirty()
656 s->dirty_page = newpage; in flash_sync_dirty()
663 uint32_t page = addr / s->pi->page_size; in flash_write8()
664 uint8_t prev = s->storage[s->cur_addr]; in flash_write8()
665 uint32_t block_protect_value = (s->block_protect3 << 3) | in flash_write8()
666 (s->block_protect2 << 2) | in flash_write8()
667 (s->block_protect1 << 1) | in flash_write8()
668 (s->block_protect0 << 0); in flash_write8()
670 if (!s->write_enable) { in flash_write8()
675 if (block_protect_value > 0) { in flash_write8()
676 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); in flash_write8()
677 uint32_t sector = addr / s->pi->sector_size; in flash_write8()
679 /* top_bottom_bit == 0 means TOP */ in flash_write8()
680 if (!s->top_bottom_bit) { in flash_write8()
681 if (s->pi->n_sectors <= sector + num_protected_sectors) { in flash_write8()
699 if (s->pi->flags & EEPROM) { in flash_write8()
700 s->storage[s->cur_addr] = data; in flash_write8()
702 s->storage[s->cur_addr] &= data; in flash_write8()
706 s->dirty_page = page; in flash_write8()
712 if (s->pi->flags == EEPROM) { in get_addr_length()
716 switch (s->cmd_in_progress) { in get_addr_length()
733 return s->four_bytes_address_mode ? 4 : 3; in get_addr_length()
742 s->cur_addr = (n == 3 ? s->ear : 0); in complete_collecting_data()
743 for (i = 0; i < n; ++i) { in complete_collecting_data()
744 s->cur_addr <<= 8; in complete_collecting_data()
745 s->cur_addr |= s->data[i]; in complete_collecting_data()
748 s->cur_addr &= s->size - 1; in complete_collecting_data()
750 s->state = STATE_IDLE; in complete_collecting_data()
752 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, in complete_collecting_data()
753 s->cur_addr); in complete_collecting_data()
755 switch (s->cmd_in_progress) { in complete_collecting_data()
762 s->state = STATE_PAGE_PROGRAM; in complete_collecting_data()
766 s->cur_addr &= ~BIT(0); in complete_collecting_data()
767 s->state = STATE_PAGE_PROGRAM; in complete_collecting_data()
781 s->state = STATE_READ; in complete_collecting_data()
790 flash_erase(s, s->cur_addr, s->cmd_in_progress); in complete_collecting_data()
793 s->status_register_write_disabled = extract32(s->data[0], 7, 1); in complete_collecting_data()
794 s->block_protect0 = extract32(s->data[0], 2, 1); in complete_collecting_data()
795 s->block_protect1 = extract32(s->data[0], 3, 1); in complete_collecting_data()
796 s->block_protect2 = extract32(s->data[0], 4, 1); in complete_collecting_data()
797 if (s->pi->flags & HAS_SR_TB) { in complete_collecting_data()
798 s->top_bottom_bit = extract32(s->data[0], 5, 1); in complete_collecting_data()
800 if (s->pi->flags & HAS_SR_BP3_BIT6) { in complete_collecting_data()
801 s->block_protect3 = extract32(s->data[0], 6, 1); in complete_collecting_data()
806 s->quad_enable = !!(s->data[1] & 0x02); in complete_collecting_data()
809 s->quad_enable = extract32(s->data[0], 6, 1); in complete_collecting_data()
812 s->quad_enable = extract32(s->data[0], 6, 1); in complete_collecting_data()
813 if (s->len > 1) { in complete_collecting_data()
814 s->volatile_cfg = s->data[1]; in complete_collecting_data()
815 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); in complete_collecting_data()
819 if (s->len > 1) { in complete_collecting_data()
820 s->quad_enable = !!(s->data[1] & 0x02); in complete_collecting_data()
826 if (s->write_enable) { in complete_collecting_data()
827 s->write_enable = false; in complete_collecting_data()
833 s->quad_enable = !!(s->data[0] & 0x02); in complete_collecting_data()
841 s->ear = s->data[0]; in complete_collecting_data()
844 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); in complete_collecting_data()
847 s->volatile_cfg = s->data[0]; in complete_collecting_data()
850 s->enh_volatile_cfg = s->data[0]; in complete_collecting_data()
855 if (s->cur_addr <= 1) { in complete_collecting_data()
856 if (s->cur_addr) { in complete_collecting_data()
857 s->data[0] = s->pi->id[2]; in complete_collecting_data()
858 s->data[1] = s->pi->id[0]; in complete_collecting_data()
860 s->data[0] = s->pi->id[0]; in complete_collecting_data()
861 s->data[1] = s->pi->id[2]; in complete_collecting_data()
863 s->pos = 0; in complete_collecting_data()
864 s->len = 2; in complete_collecting_data()
865 s->data_read_loop = true; in complete_collecting_data()
866 s->state = STATE_READING_DATA; in complete_collecting_data()
873 "M25P80: Read id (command 0x90/0xAB) is not supported" in complete_collecting_data()
879 s->state = STATE_READING_SFDP; in complete_collecting_data()
889 s->cmd_in_progress = NOP; in reset_memory()
890 s->cur_addr = 0; in reset_memory()
891 s->ear = 0; in reset_memory()
892 s->four_bytes_address_mode = false; in reset_memory()
893 s->len = 0; in reset_memory()
894 s->needed_bytes = 0; in reset_memory()
895 s->pos = 0; in reset_memory()
896 s->state = STATE_IDLE; in reset_memory()
897 s->write_enable = false; in reset_memory()
898 s->reset_enable = false; in reset_memory()
899 s->quad_enable = false; in reset_memory()
900 s->aai_enable = false; in reset_memory()
904 s->volatile_cfg = 0; in reset_memory()
905 s->volatile_cfg |= VCFG_DUMMY; in reset_memory()
906 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; in reset_memory()
907 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) in reset_memory()
909 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; in reset_memory()
911 s->volatile_cfg |= deposit32(s->volatile_cfg, in reset_memory()
914 extract32(s->nonvolatile_cfg, in reset_memory()
919 s->enh_volatile_cfg = 0; in reset_memory()
920 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; in reset_memory()
921 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; in reset_memory()
922 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; in reset_memory()
923 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { in reset_memory()
924 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; in reset_memory()
926 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { in reset_memory()
927 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; in reset_memory()
929 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { in reset_memory()
930 s->four_bytes_address_mode = true; in reset_memory()
932 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { in reset_memory()
933 s->ear = s->size / MAX_3BYTES_SIZE - 1; in reset_memory()
937 s->volatile_cfg = 0x7; in reset_memory()
940 s->spansion_cr1v = s->spansion_cr1nv; in reset_memory()
941 s->spansion_cr2v = s->spansion_cr2nv; in reset_memory()
942 s->spansion_cr3v = s->spansion_cr3nv; in reset_memory()
943 s->spansion_cr4v = s->spansion_cr4nv; in reset_memory()
944 s->quad_enable = extract32(s->spansion_cr1v, in reset_memory()
948 s->four_bytes_address_mode = extract32(s->spansion_cr2v, in reset_memory()
962 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { in numonyx_mode()
964 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { in numonyx_mode()
978 num_dummies = extract32(s->volatile_cfg, 4, 4); in numonyx_extract_cfg_num_dummies()
980 if (num_dummies == 0x0 || num_dummies == 0xf) { in numonyx_extract_cfg_num_dummies()
981 switch (s->cmd_in_progress) { in numonyx_extract_cfg_num_dummies()
997 s->needed_bytes = get_addr_length(s); in decode_fast_read_cmd()
999 /* Dummy cycles - modeled with bytes writes instead of bits */ in decode_fast_read_cmd()
1001 s->needed_bytes += 1; in decode_fast_read_cmd()
1004 s->needed_bytes += 8; in decode_fast_read_cmd()
1007 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); in decode_fast_read_cmd()
1010 if (extract32(s->volatile_cfg, 6, 2) == 1) { in decode_fast_read_cmd()
1011 s->needed_bytes += 6; in decode_fast_read_cmd()
1013 s->needed_bytes += 8; in decode_fast_read_cmd()
1017 s->needed_bytes += extract32(s->spansion_cr2v, in decode_fast_read_cmd()
1033 s->needed_bytes += 1; in decode_fast_read_cmd()
1038 s->pos = 0; in decode_fast_read_cmd()
1039 s->len = 0; in decode_fast_read_cmd()
1040 s->state = STATE_COLLECTING_DATA; in decode_fast_read_cmd()
1045 s->needed_bytes = get_addr_length(s); in decode_dio_read_cmd()
1049 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; in decode_dio_read_cmd()
1052 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; in decode_dio_read_cmd()
1053 s->needed_bytes += extract32(s->spansion_cr2v, in decode_dio_read_cmd()
1059 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); in decode_dio_read_cmd()
1062 switch (extract32(s->volatile_cfg, 6, 2)) { in decode_dio_read_cmd()
1064 s->needed_bytes += 6; in decode_dio_read_cmd()
1067 s->needed_bytes += 8; in decode_dio_read_cmd()
1070 s->needed_bytes += 4; in decode_dio_read_cmd()
1082 s->needed_bytes += 1; in decode_dio_read_cmd()
1087 s->pos = 0; in decode_dio_read_cmd()
1088 s->len = 0; in decode_dio_read_cmd()
1089 s->state = STATE_COLLECTING_DATA; in decode_dio_read_cmd()
1094 s->needed_bytes = get_addr_length(s); in decode_qio_read_cmd()
1098 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; in decode_qio_read_cmd()
1099 s->needed_bytes += 4; in decode_qio_read_cmd()
1102 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; in decode_qio_read_cmd()
1103 s->needed_bytes += extract32(s->spansion_cr2v, in decode_qio_read_cmd()
1109 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); in decode_qio_read_cmd()
1112 switch (extract32(s->volatile_cfg, 6, 2)) { in decode_qio_read_cmd()
1114 s->needed_bytes += 4; in decode_qio_read_cmd()
1117 s->needed_bytes += 8; in decode_qio_read_cmd()
1120 s->needed_bytes += 6; in decode_qio_read_cmd()
1135 s->needed_bytes += 3; in decode_qio_read_cmd()
1140 s->pos = 0; in decode_qio_read_cmd()
1141 s->len = 0; in decode_qio_read_cmd()
1142 s->state = STATE_COLLECTING_DATA; in decode_qio_read_cmd()
1154 s->cmd_in_progress = value; in decode_new_cmd()
1158 s->reset_enable = false; in decode_new_cmd()
1161 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { in decode_new_cmd()
1179 s->needed_bytes = get_addr_length(s); in decode_new_cmd()
1180 s->pos = 0; in decode_new_cmd()
1181 s->len = 0; in decode_new_cmd()
1182 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1187 s->needed_bytes = get_addr_length(s); in decode_new_cmd()
1188 s->pos = 0; in decode_new_cmd()
1189 s->len = 0; in decode_new_cmd()
1190 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1193 "DIO or QIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1198 s->needed_bytes = get_addr_length(s); in decode_new_cmd()
1199 s->pos = 0; in decode_new_cmd()
1200 s->len = 0; in decode_new_cmd()
1201 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1204 "QIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1211 s->needed_bytes = get_addr_length(s); in decode_new_cmd()
1212 s->pos = 0; in decode_new_cmd()
1213 s->len = 0; in decode_new_cmd()
1214 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1217 "DIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1231 "QIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1240 "DIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1250 "QIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1260 "DIO mode\n", s->cmd_in_progress); in decode_new_cmd()
1272 if ((s->wp_level == 0 && s->status_register_write_disabled) in decode_new_cmd()
1273 || !s->write_enable) { in decode_new_cmd()
1281 s->needed_bytes = 2; in decode_new_cmd()
1282 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1285 s->needed_bytes = 2; in decode_new_cmd()
1286 s->state = STATE_COLLECTING_VAR_LEN_DATA; in decode_new_cmd()
1289 s->needed_bytes = 2; in decode_new_cmd()
1290 s->state = STATE_COLLECTING_VAR_LEN_DATA; in decode_new_cmd()
1293 s->needed_bytes = 1; in decode_new_cmd()
1294 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1296 s->pos = 0; in decode_new_cmd()
1306 if ((s->wp_level == 0 && s->status_register_write_disabled) in decode_new_cmd()
1307 || !s->write_enable) { in decode_new_cmd()
1315 s->needed_bytes = 1; in decode_new_cmd()
1316 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1317 s->pos = 0; in decode_new_cmd()
1324 s->write_enable = false; in decode_new_cmd()
1326 s->aai_enable = false; in decode_new_cmd()
1330 s->write_enable = true; in decode_new_cmd()
1334 s->data[0] = (!!s->write_enable) << 1; in decode_new_cmd()
1335 s->data[0] |= (!!s->status_register_write_disabled) << 7; in decode_new_cmd()
1336 s->data[0] |= (!!s->block_protect0) << 2; in decode_new_cmd()
1337 s->data[0] |= (!!s->block_protect1) << 3; in decode_new_cmd()
1338 s->data[0] |= (!!s->block_protect2) << 4; in decode_new_cmd()
1339 if (s->pi->flags & HAS_SR_TB) { in decode_new_cmd()
1340 s->data[0] |= (!!s->top_bottom_bit) << 5; in decode_new_cmd()
1342 if (s->pi->flags & HAS_SR_BP3_BIT6) { in decode_new_cmd()
1343 s->data[0] |= (!!s->block_protect3) << 6; in decode_new_cmd()
1347 s->data[0] |= (!!s->quad_enable) << 6; in decode_new_cmd()
1350 s->data[0] |= (!!s->aai_enable) << 6; in decode_new_cmd()
1353 s->pos = 0; in decode_new_cmd()
1354 s->len = 1; in decode_new_cmd()
1355 s->data_read_loop = true; in decode_new_cmd()
1356 s->state = STATE_READING_DATA; in decode_new_cmd()
1360 s->data[0] = FSR_FLASH_READY; in decode_new_cmd()
1361 if (s->four_bytes_address_mode) { in decode_new_cmd()
1362 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; in decode_new_cmd()
1364 s->pos = 0; in decode_new_cmd()
1365 s->len = 1; in decode_new_cmd()
1366 s->data_read_loop = true; in decode_new_cmd()
1367 s->state = STATE_READING_DATA; in decode_new_cmd()
1373 for (i = 0; i < s->pi->id_len; i++) { in decode_new_cmd()
1374 s->data[i] = s->pi->id[i]; in decode_new_cmd()
1377 s->data[i] = 0; in decode_new_cmd()
1380 s->len = SPI_NOR_MAX_ID_LEN; in decode_new_cmd()
1381 s->pos = 0; in decode_new_cmd()
1382 s->state = STATE_READING_DATA; in decode_new_cmd()
1390 s->data[0] = s->volatile_cfg & 0xFF; in decode_new_cmd()
1391 s->data[0] |= (!!s->four_bytes_address_mode) << 5; in decode_new_cmd()
1392 s->pos = 0; in decode_new_cmd()
1393 s->len = 1; in decode_new_cmd()
1394 s->state = STATE_READING_DATA; in decode_new_cmd()
1399 if (s->write_enable) { in decode_new_cmd()
1401 flash_erase(s, 0, BULK_ERASE); in decode_new_cmd()
1410 s->four_bytes_address_mode = true; in decode_new_cmd()
1413 s->four_bytes_address_mode = false; in decode_new_cmd()
1417 s->data[0] = s->ear; in decode_new_cmd()
1418 s->pos = 0; in decode_new_cmd()
1419 s->len = 1; in decode_new_cmd()
1420 s->state = STATE_READING_DATA; in decode_new_cmd()
1424 if (s->write_enable) { in decode_new_cmd()
1425 s->needed_bytes = 1; in decode_new_cmd()
1426 s->pos = 0; in decode_new_cmd()
1427 s->len = 0; in decode_new_cmd()
1428 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1432 s->data[0] = s->nonvolatile_cfg & 0xFF; in decode_new_cmd()
1433 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; in decode_new_cmd()
1434 s->pos = 0; in decode_new_cmd()
1435 s->len = 2; in decode_new_cmd()
1436 s->state = STATE_READING_DATA; in decode_new_cmd()
1439 if (s->write_enable && get_man(s) == MAN_NUMONYX) { in decode_new_cmd()
1440 s->needed_bytes = 2; in decode_new_cmd()
1441 s->pos = 0; in decode_new_cmd()
1442 s->len = 0; in decode_new_cmd()
1443 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1447 s->data[0] = s->volatile_cfg & 0xFF; in decode_new_cmd()
1448 s->pos = 0; in decode_new_cmd()
1449 s->len = 1; in decode_new_cmd()
1450 s->state = STATE_READING_DATA; in decode_new_cmd()
1453 if (s->write_enable) { in decode_new_cmd()
1454 s->needed_bytes = 1; in decode_new_cmd()
1455 s->pos = 0; in decode_new_cmd()
1456 s->len = 0; in decode_new_cmd()
1457 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1461 s->data[0] = s->enh_volatile_cfg & 0xFF; in decode_new_cmd()
1462 s->pos = 0; in decode_new_cmd()
1463 s->len = 1; in decode_new_cmd()
1464 s->state = STATE_READING_DATA; in decode_new_cmd()
1467 if (s->write_enable) { in decode_new_cmd()
1468 s->needed_bytes = 1; in decode_new_cmd()
1469 s->pos = 0; in decode_new_cmd()
1470 s->len = 0; in decode_new_cmd()
1471 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1475 s->reset_enable = true; in decode_new_cmd()
1478 if (s->reset_enable) { in decode_new_cmd()
1485 s->data[0] = (!!s->quad_enable) << 1; in decode_new_cmd()
1486 s->pos = 0; in decode_new_cmd()
1487 s->len = 1; in decode_new_cmd()
1488 s->state = STATE_READING_DATA; in decode_new_cmd()
1491 s->quad_enable = true; in decode_new_cmd()
1494 s->data[0] = (!!s->quad_enable) << 1; in decode_new_cmd()
1495 s->pos = 0; in decode_new_cmd()
1496 s->len = 1; in decode_new_cmd()
1497 s->state = STATE_READING_DATA; in decode_new_cmd()
1504 s->quad_enable = false; in decode_new_cmd()
1508 if (s->write_enable) { in decode_new_cmd()
1509 if (s->aai_enable) { in decode_new_cmd()
1510 s->state = STATE_PAGE_PROGRAM; in decode_new_cmd()
1512 s->aai_enable = true; in decode_new_cmd()
1513 s->needed_bytes = get_addr_length(s); in decode_new_cmd()
1514 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1525 if (s->pi->sfdp_read) { in decode_new_cmd()
1526 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ in decode_new_cmd()
1527 s->pos = 0; in decode_new_cmd()
1528 s->len = 0; in decode_new_cmd()
1529 s->state = STATE_COLLECTING_DATA; in decode_new_cmd()
1535 s->pos = 0; in decode_new_cmd()
1536 s->len = 1; in decode_new_cmd()
1537 s->state = STATE_READING_DATA; in decode_new_cmd()
1538 s->data_read_loop = true; in decode_new_cmd()
1539 s->data[0] = 0; in decode_new_cmd()
1550 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { in m25p80_cs()
1553 s->len = 0; in m25p80_cs()
1554 s->pos = 0; in m25p80_cs()
1555 s->state = STATE_IDLE; in m25p80_cs()
1556 flash_sync_dirty(s, -1); in m25p80_cs()
1557 s->data_read_loop = false; in m25p80_cs()
1562 return 0; in m25p80_cs()
1568 uint32_t r = 0; in m25p80_transfer8()
1570 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, in m25p80_transfer8()
1571 s->cur_addr, (uint8_t)tx); in m25p80_transfer8()
1573 switch (s->state) { in m25p80_transfer8()
1576 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); in m25p80_transfer8()
1577 flash_write8(s, s->cur_addr, (uint8_t)tx); in m25p80_transfer8()
1578 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); in m25p80_transfer8()
1580 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { in m25p80_transfer8()
1583 * unprotected memory address is reached. The Write-Enable-Latch in m25p80_transfer8()
1586 s->write_enable = false; in m25p80_transfer8()
1587 s->aai_enable = false; in m25p80_transfer8()
1593 r = s->storage[s->cur_addr]; in m25p80_transfer8()
1594 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); in m25p80_transfer8()
1595 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); in m25p80_transfer8()
1601 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { in m25p80_transfer8()
1606 s->len = s->pos = 0; in m25p80_transfer8()
1607 s->state = STATE_IDLE; in m25p80_transfer8()
1611 s->data[s->len] = (uint8_t)tx; in m25p80_transfer8()
1612 s->len++; in m25p80_transfer8()
1614 if (s->len == s->needed_bytes) { in m25p80_transfer8()
1621 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { in m25p80_transfer8()
1626 s->len = s->pos = 0; in m25p80_transfer8()
1627 s->state = STATE_IDLE; in m25p80_transfer8()
1631 r = s->data[s->pos]; in m25p80_transfer8()
1632 trace_m25p80_read_data(s, s->pos, (uint8_t)r); in m25p80_transfer8()
1633 s->pos++; in m25p80_transfer8()
1634 if (s->pos == s->len) { in m25p80_transfer8()
1635 s->pos = 0; in m25p80_transfer8()
1636 if (!s->data_read_loop) { in m25p80_transfer8()
1637 s->state = STATE_IDLE; in m25p80_transfer8()
1642 assert(s->pi->sfdp_read); in m25p80_transfer8()
1643 r = s->pi->sfdp_read(s->cur_addr); in m25p80_transfer8()
1644 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); in m25p80_transfer8()
1645 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); in m25p80_transfer8()
1661 assert(n == 0); in m25p80_write_protect_pin_irq_handler()
1662 s->wp_level = !!level; in m25p80_write_protect_pin_irq_handler()
1671 s->pi = mc->pi; in m25p80_realize()
1673 s->size = s->pi->sector_size * s->pi->n_sectors; in m25p80_realize()
1674 s->dirty_page = -1; in m25p80_realize()
1676 if (s->blk) { in m25p80_realize()
1678 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); in m25p80_realize()
1679 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); in m25p80_realize()
1680 if (ret < 0) { in m25p80_realize()
1685 s->storage = blk_blockalign(s->blk, s->size); in m25p80_realize()
1687 if (!blk_check_size_and_read_all(s->blk, DEVICE(s), in m25p80_realize()
1688 s->storage, s->size, errp)) { in m25p80_realize()
1693 s->storage = blk_blockalign(NULL, s->size); in m25p80_realize()
1694 memset(s->storage, 0xFF, s->size); in m25p80_realize()
1705 s->wp_level = true; in m25p80_reset()
1706 s->status_register_write_disabled = false; in m25p80_reset()
1707 s->block_protect0 = false; in m25p80_reset()
1708 s->block_protect1 = false; in m25p80_reset()
1709 s->block_protect2 = false; in m25p80_reset()
1710 s->block_protect3 = false; in m25p80_reset()
1711 s->top_bottom_bit = false; in m25p80_reset()
1718 flash_sync_dirty((Flash *)opaque, -1); in m25p80_pre_save()
1720 return 0; in m25p80_pre_save()
1725 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
1726 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1727 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1728 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1729 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1730 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1739 s->data_read_loop = false; in m25p80_pre_load()
1740 return 0; in m25p80_pre_load()
1747 return s->data_read_loop; in m25p80_data_read_loop_needed()
1765 return s->aai_enable; in m25p80_aai_enable_needed()
1783 return !s->wp_level || s->status_register_write_disabled; in m25p80_wp_level_srwd_needed()
1802 return s->block_protect0 || in m25p80_block_protect_needed()
1803 s->block_protect1 || in m25p80_block_protect_needed()
1804 s->block_protect2 || in m25p80_block_protect_needed()
1805 s->block_protect3 || in m25p80_block_protect_needed()
1806 s->top_bottom_bit; in m25p80_block_protect_needed()
1826 .version_id = 0,
1827 .minimum_version_id = 0,
1867 k->realize = m25p80_realize; in m25p80_class_init()
1868 k->transfer = m25p80_transfer8; in m25p80_class_init()
1869 k->set_cs = m25p80_cs; in m25p80_class_init()
1870 k->cs_polarity = SSI_CS_LOW; in m25p80_class_init()
1871 dc->vmsd = &vmstate_m25p80; in m25p80_class_init()
1874 mc->pi = data; in m25p80_class_init()
1890 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { in m25p80_register_types()
1905 return M25P80(dev)->blk; in type_init()