Lines Matching refs:tx_sample_size

72     uint8_t tx_sample_size;  member
181             switch (channel->tx_sample_size) {  in pl041_fifo1_write()
216                 switch (channel->tx_sample_size) {  in pl041_fifo1_write()
415             channel->tx_sample_size = 16;  in pl041_write()
418             channel->tx_sample_size = 18;  in pl041_write()
421             channel->tx_sample_size = 20;  in pl041_write()
424             channel->tx_sample_size = 12;  in pl041_write()
430         DBG_L1("TX sample width = %i\n", channel->tx_sample_size);  in pl041_write()
434             if ((channel->tx_sample_size == 18) ||  in pl041_write()
435                 (channel->tx_sample_size == 20)) {  in pl041_write()
602         VMSTATE_UINT8(tx_sample_size, pl041_channel),