Lines Matching +full:d +full:- +full:- +full:- +full:- +full:- +full:1
22 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
30 #include "intel-hda.h"
32 #include "intel-hda-defs.h"
37 /* --------------------------------------------------------------------- */
41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
56 bus->response = response; in hda_codec_bus_init()
57 bus->xfer = xfer; in hda_codec_bus_init()
62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); in hda_codec_dev_realize()
66 if (dev->cad == -1) { in hda_codec_dev_realize()
67 dev->cad = bus->next_cad; in hda_codec_dev_realize()
69 if (dev->cad >= 15) { in hda_codec_dev_realize()
73 bus->next_cad = dev->cad + 1; in hda_codec_dev_realize()
74 cdc->init(dev, errp); in hda_codec_dev_realize()
82 if (cdc->exit) { in hda_codec_dev_unrealize()
83 cdc->exit(dev); in hda_codec_dev_unrealize()
92 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { in hda_codec_find()
93 DeviceState *qdev = kid->child; in hda_codec_find()
95 if (cdev->cad == cad) { in hda_codec_find()
104 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in hda_codec_response()
105 bus->response(dev, solicited, response); in hda_codec_response()
111 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in hda_codec_xfer()
112 return bus->xfer(dev, stnr, output, buf, len); in hda_codec_xfer()
115 /* --------------------------------------------------------------------- */
203 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
213 uint32_t wclear; /* write 1 to clear bits */
217 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
218 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
221 /* --------------------------------------------------------------------- */
228 static void intel_hda_update_int_sts(IntelHDAState *d) in intel_hda_update_int_sts() argument
234 if (d->rirb_sts & ICH6_RBSTS_IRQ) { in intel_hda_update_int_sts()
235 sts |= (1 << 30); in intel_hda_update_int_sts()
237 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { in intel_hda_update_int_sts()
238 sts |= (1 << 30); in intel_hda_update_int_sts()
240 if (d->state_sts & d->wake_en) { in intel_hda_update_int_sts()
241 sts |= (1 << 30); in intel_hda_update_int_sts()
247 if (d->st[i].ctl & (1 << 26)) { in intel_hda_update_int_sts()
248 sts |= (1 << i); in intel_hda_update_int_sts()
253 if (sts & d->int_ctl) { in intel_hda_update_int_sts()
254 sts |= (1U << 31); in intel_hda_update_int_sts()
257 d->int_sts = sts; in intel_hda_update_int_sts()
260 static void intel_hda_update_irq(IntelHDAState *d) in intel_hda_update_irq() argument
262 bool msi = msi_enabled(&d->pci); in intel_hda_update_irq()
265 intel_hda_update_int_sts(d); in intel_hda_update_irq()
266 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { in intel_hda_update_irq()
267 level = 1; in intel_hda_update_irq()
271 dprint(d, 2, "%s: level %d [%s]\n", __func__, in intel_hda_update_irq()
275 msi_notify(&d->pci, 0); in intel_hda_update_irq()
278 pci_set_irq(&d->pci, level); in intel_hda_update_irq()
282 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) in intel_hda_send_command() argument
289 if (verb & (1 << 27)) { in intel_hda_send_command()
291 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); in intel_hda_send_command()
292 return -1; in intel_hda_send_command()
297 codec = hda_codec_find(&d->codecs, cad); in intel_hda_send_command()
299 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); in intel_hda_send_command()
300 return -1; in intel_hda_send_command()
303 cdc->command(codec, nid, data); in intel_hda_send_command()
307 static void intel_hda_corb_run(IntelHDAState *d) in intel_hda_corb_run() argument
312 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_corb_run()
313 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); in intel_hda_corb_run()
314 intel_hda_send_command(d, d->icw); in intel_hda_corb_run()
319 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { in intel_hda_corb_run()
320 dprint(d, 2, "%s: !run\n", __func__); in intel_hda_corb_run()
323 if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_corb_run()
324 dprint(d, 2, "%s: corb ring empty\n", __func__); in intel_hda_corb_run()
327 if (d->rirb_count == d->rirb_cnt) { in intel_hda_corb_run()
328 dprint(d, 2, "%s: rirb count reached\n", __func__); in intel_hda_corb_run()
332 rp = (d->corb_rp + 1) & 0xff; in intel_hda_corb_run()
333 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); in intel_hda_corb_run()
334 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED); in intel_hda_corb_run()
335 d->corb_rp = rp; in intel_hda_corb_run()
337 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); in intel_hda_corb_run()
338 intel_hda_send_command(d, verb); in intel_hda_corb_run()
345 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in intel_hda_response()
346 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); in intel_hda_response() local
351 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_response()
352 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", in intel_hda_response()
353 __func__, response, dev->cad); in intel_hda_response()
354 d->irr = response; in intel_hda_response()
355 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); in intel_hda_response()
356 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); in intel_hda_response()
360 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { in intel_hda_response()
361 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); in intel_hda_response()
365 ex = (solicited ? 0 : (1 << 4)) | dev->cad; in intel_hda_response()
366 wp = (d->rirb_wp + 1) & 0xff; in intel_hda_response()
367 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); in intel_hda_response()
368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); in intel_hda_response()
369 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); in intel_hda_response()
370 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) { in intel_hda_response()
371 d->rirb_sts |= ICH6_RBSTS_OVERRUN; in intel_hda_response()
372 intel_hda_update_irq(d); in intel_hda_response()
374 d->rirb_wp = wp; in intel_hda_response()
376 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", in intel_hda_response()
379 d->rirb_count++; in intel_hda_response()
380 if (d->rirb_count == d->rirb_cnt) { in intel_hda_response()
381 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); in intel_hda_response()
382 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
383 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
384 intel_hda_update_irq(d); in intel_hda_response()
386 } else if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_response()
387 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, in intel_hda_response()
388 d->rirb_count, d->rirb_cnt); in intel_hda_response()
389 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
390 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
391 intel_hda_update_irq(d); in intel_hda_response()
400 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in intel_hda_xfer()
401 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); in intel_hda_xfer() local
407 st = output ? d->st + 4 : d->st; in intel_hda_xfer()
417 if (st->bpl == NULL) { in intel_hda_xfer()
422 s = st->bentries; in intel_hda_xfer()
423 while (left > 0 && s-- > 0) { in intel_hda_xfer()
425 if (copy > st->bsize - st->lpib) in intel_hda_xfer()
426 copy = st->bsize - st->lpib; in intel_hda_xfer()
427 if (copy > st->bpl[st->be].len - st->bp) in intel_hda_xfer()
428 copy = st->bpl[st->be].len - st->bp; in intel_hda_xfer()
430 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", in intel_hda_xfer()
431 st->be, st->bp, st->bpl[st->be].len, copy); in intel_hda_xfer()
433 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, in intel_hda_xfer()
435 st->lpib += copy; in intel_hda_xfer()
436 st->bp += copy; in intel_hda_xfer()
438 left -= copy; in intel_hda_xfer()
440 if (st->bpl[st->be].len == st->bp) { in intel_hda_xfer()
442 if (st->bpl[st->be].flags & 0x01) { in intel_hda_xfer()
445 st->bp = 0; in intel_hda_xfer()
446 st->be++; in intel_hda_xfer()
447 if (st->be == st->bentries) { in intel_hda_xfer()
449 st->be = 0; in intel_hda_xfer()
450 st->lpib = 0; in intel_hda_xfer()
454 if (d->dp_lbase & 0x01) { in intel_hda_xfer()
455 s = st - d->st; in intel_hda_xfer()
456 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); in intel_hda_xfer()
457 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); in intel_hda_xfer()
459 dprint(d, 3, "dma: --\n"); in intel_hda_xfer()
462 st->ctl |= (1 << 26); /* buffer completion interrupt */ in intel_hda_xfer()
463 intel_hda_update_irq(d); in intel_hda_xfer()
468 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) in intel_hda_parse_bdl() argument
474 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); in intel_hda_parse_bdl()
475 st->bentries = st->lvi +1; in intel_hda_parse_bdl()
476 g_free(st->bpl); in intel_hda_parse_bdl()
477 st->bpl = g_new(bpl, st->bentries); in intel_hda_parse_bdl()
478 for (i = 0; i < st->bentries; i++, addr += 16) { in intel_hda_parse_bdl()
479 pci_dma_read(&d->pci, addr, buf, 16); in intel_hda_parse_bdl()
480 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); in intel_hda_parse_bdl()
481 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); in intel_hda_parse_bdl()
482 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); in intel_hda_parse_bdl()
483 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", in intel_hda_parse_bdl()
484 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); in intel_hda_parse_bdl()
487 st->bsize = st->cbl; in intel_hda_parse_bdl()
488 st->lpib = 0; in intel_hda_parse_bdl()
489 st->be = 0; in intel_hda_parse_bdl()
490 st->bp = 0; in intel_hda_parse_bdl()
493 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) in intel_hda_notify_codecs() argument
498 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_notify_codecs()
499 DeviceState *qdev = kid->child; in intel_hda_notify_codecs()
504 if (cdc->stream) { in intel_hda_notify_codecs()
505 cdc->stream(cdev, stream, running, output); in intel_hda_notify_codecs()
510 /* --------------------------------------------------------------------- */
512 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_g_ctl() argument
514 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { in intel_hda_set_g_ctl()
515 device_cold_reset(DEVICE(d)); in intel_hda_set_g_ctl()
519 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_wake_en() argument
521 intel_hda_update_irq(d); in intel_hda_set_wake_en()
524 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_state_sts() argument
526 intel_hda_update_irq(d); in intel_hda_set_state_sts()
529 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_int_ctl() argument
531 intel_hda_update_irq(d); in intel_hda_set_int_ctl()
534 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) in intel_hda_get_wall_clk() argument
538 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; in intel_hda_get_wall_clk()
539 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ in intel_hda_get_wall_clk()
542 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_corb_wp() argument
544 intel_hda_corb_run(d); in intel_hda_set_corb_wp()
547 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_corb_ctl() argument
549 intel_hda_corb_run(d); in intel_hda_set_corb_ctl()
552 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_rirb_wp() argument
554 if (d->rirb_wp & ICH6_RIRBWP_RST) { in intel_hda_set_rirb_wp()
555 d->rirb_wp = 0; in intel_hda_set_rirb_wp()
559 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_rirb_sts() argument
561 intel_hda_update_irq(d); in intel_hda_set_rirb_sts()
563 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { in intel_hda_set_rirb_sts()
565 d->rirb_count = 0; in intel_hda_set_rirb_sts()
566 intel_hda_corb_run(d); in intel_hda_set_rirb_sts()
570 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_ics() argument
572 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_set_ics()
573 intel_hda_corb_run(d); in intel_hda_set_ics()
577 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_st_ctl() argument
579 bool output = reg->stream >= 4; in intel_hda_set_st_ctl()
580 IntelHDAStream *st = d->st + reg->stream; in intel_hda_set_st_ctl()
582 if (st->ctl & 0x01) { in intel_hda_set_st_ctl()
584 dprint(d, 1, "st #%d: reset\n", reg->stream); in intel_hda_set_st_ctl()
585 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; in intel_hda_set_st_ctl()
587 if ((st->ctl & 0x02) != (old & 0x02)) { in intel_hda_set_st_ctl()
588 uint32_t stnr = (st->ctl >> 20) & 0x0f; in intel_hda_set_st_ctl()
590 if (st->ctl & 0x02) { in intel_hda_set_st_ctl()
592 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", in intel_hda_set_st_ctl()
593 reg->stream, stnr, st->cbl); in intel_hda_set_st_ctl()
594 intel_hda_parse_bdl(d, st); in intel_hda_set_st_ctl()
595 intel_hda_notify_codecs(d, stnr, true, output); in intel_hda_set_st_ctl()
598 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); in intel_hda_set_st_ctl()
599 intel_hda_notify_codecs(d, stnr, false, output); in intel_hda_set_st_ctl()
602 intel_hda_update_irq(d); in intel_hda_set_st_ctl()
605 /* --------------------------------------------------------------------- */
618 .size = 1,
622 .size = 1,
623 .reset = 1,
710 .size = 1,
717 .size = 1,
724 .size = 1,
755 .size = 1,
761 .size = 1,
769 .size = 1,
819 .size = 1, \
828 .size = 1, \
885 HDA_STREAM("IN", 1)
896 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) in intel_hda_reg_find() argument
904 if (reg->name == NULL) { in intel_hda_reg_find()
910 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); in intel_hda_reg_find()
914 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) in intel_hda_reg_addr() argument
916 uint8_t *addr = (void*)d; in intel_hda_reg_addr()
918 addr += reg->offset; in intel_hda_reg_addr()
922 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, in intel_hda_reg_write() argument
931 if (!reg->wmask) { in intel_hda_reg_write()
932 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", in intel_hda_reg_write()
933 reg->name); in intel_hda_reg_write()
937 if (d->debug) { in intel_hda_reg_write()
939 if (d->last_write && d->last_reg == reg && d->last_val == val) { in intel_hda_reg_write()
940 d->repeat_count++; in intel_hda_reg_write()
941 if (d->last_sec != now) { in intel_hda_reg_write()
942 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
943 d->last_sec = now; in intel_hda_reg_write()
944 d->repeat_count = 0; in intel_hda_reg_write()
947 if (d->repeat_count) { in intel_hda_reg_write()
948 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
950 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); in intel_hda_reg_write()
951 d->last_write = 1; in intel_hda_reg_write()
952 d->last_reg = reg; in intel_hda_reg_write()
953 d->last_val = val; in intel_hda_reg_write()
954 d->last_sec = now; in intel_hda_reg_write()
955 d->repeat_count = 0; in intel_hda_reg_write()
958 assert(reg->offset != 0); in intel_hda_reg_write()
960 addr = intel_hda_reg_addr(d, reg); in intel_hda_reg_write()
963 if (reg->shift) { in intel_hda_reg_write()
964 val <<= reg->shift; in intel_hda_reg_write()
965 wmask <<= reg->shift; in intel_hda_reg_write()
967 wmask &= reg->wmask; in intel_hda_reg_write()
970 *addr &= ~(val & reg->wclear); in intel_hda_reg_write()
972 if (reg->whandler) { in intel_hda_reg_write()
973 reg->whandler(d, reg, old); in intel_hda_reg_write()
977 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, in intel_hda_reg_read() argument
986 if (reg->rhandler) { in intel_hda_reg_read()
987 reg->rhandler(d, reg); in intel_hda_reg_read()
990 if (reg->offset == 0) { in intel_hda_reg_read()
991 /* constant read-only register */ in intel_hda_reg_read()
992 ret = reg->reset; in intel_hda_reg_read()
994 addr = intel_hda_reg_addr(d, reg); in intel_hda_reg_read()
996 if (reg->shift) { in intel_hda_reg_read()
997 ret >>= reg->shift; in intel_hda_reg_read()
1001 if (d->debug) { in intel_hda_reg_read()
1003 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { in intel_hda_reg_read()
1004 d->repeat_count++; in intel_hda_reg_read()
1005 if (d->last_sec != now) { in intel_hda_reg_read()
1006 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1007 d->last_sec = now; in intel_hda_reg_read()
1008 d->repeat_count = 0; in intel_hda_reg_read()
1011 if (d->repeat_count) { in intel_hda_reg_read()
1012 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1014 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); in intel_hda_reg_read()
1015 d->last_write = 0; in intel_hda_reg_read()
1016 d->last_reg = reg; in intel_hda_reg_read()
1017 d->last_val = ret; in intel_hda_reg_read()
1018 d->last_sec = now; in intel_hda_reg_read()
1019 d->repeat_count = 0; in intel_hda_reg_read()
1025 static void intel_hda_regs_reset(IntelHDAState *d) in intel_hda_regs_reset() argument
1037 addr = intel_hda_reg_addr(d, regtab + i); in intel_hda_regs_reset()
1042 /* --------------------------------------------------------------------- */
1047 IntelHDAState *d = opaque; in intel_hda_mmio_write() local
1048 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); in intel_hda_mmio_write()
1050 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); in intel_hda_mmio_write()
1055 IntelHDAState *d = opaque; in intel_hda_mmio_read() local
1056 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); in intel_hda_mmio_read()
1058 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); in intel_hda_mmio_read()
1065 .min_access_size = 1,
1071 /* --------------------------------------------------------------------- */
1076 IntelHDAState *d = INTEL_HDA(dev); in intel_hda_reset() local
1079 intel_hda_regs_reset(d); in intel_hda_reset()
1080 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in intel_hda_reset()
1082 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_reset()
1083 DeviceState *qdev = kid->child; in intel_hda_reset()
1085 d->state_sts |= (1 << cdev->cad); in intel_hda_reset()
1087 intel_hda_update_irq(d); in intel_hda_reset()
1092 IntelHDAState *d = INTEL_HDA(pci); in intel_hda_realize() local
1093 uint8_t *conf = d->pci.config; in intel_hda_realize()
1097 d->name = object_get_typename(OBJECT(d)); in intel_hda_realize()
1099 pci_config_set_interrupt_pin(conf, 1); in intel_hda_realize()
1101 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ in intel_hda_realize()
1104 if (d->msi != ON_OFF_AUTO_OFF) { in intel_hda_realize()
1105 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, in intel_hda_realize()
1106 1, true, false, &err); in intel_hda_realize()
1107 /* Any error other than -ENOTSUP(board's MSI support is broken) in intel_hda_realize()
1109 assert(!ret || ret == -ENOTSUP); in intel_hda_realize()
1110 if (ret && d->msi == ON_OFF_AUTO_ON) { in intel_hda_realize()
1117 assert(!err || d->msi == ON_OFF_AUTO_AUTO); in intel_hda_realize()
1122 memory_region_init(&d->container, OBJECT(d), in intel_hda_realize()
1123 "intel-hda-container", 0x4000); in intel_hda_realize()
1124 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, in intel_hda_realize()
1125 "intel-hda", 0x2000); in intel_hda_realize()
1126 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); in intel_hda_realize()
1127 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", in intel_hda_realize()
1128 &d->mmio, 0, 0x2000); in intel_hda_realize()
1129 memory_region_add_subregion(&d->container, 0x2000, &d->alias); in intel_hda_realize()
1130 pci_register_bar(&d->pci, 0, 0, &d->container); in intel_hda_realize()
1132 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), in intel_hda_realize()
1138 IntelHDAState *d = INTEL_HDA(pci); in intel_hda_exit() local
1140 msi_uninit(&d->pci); in intel_hda_exit()
1145 IntelHDAState* d = opaque; in intel_hda_post_load() local
1148 dprint(d, 1, "%s\n", __func__); in intel_hda_post_load()
1149 for (i = 0; i < ARRAY_SIZE(d->st); i++) { in intel_hda_post_load()
1150 if (d->st[i].ctl & 0x02) { in intel_hda_post_load()
1151 intel_hda_parse_bdl(d, &d->st[i]); in intel_hda_post_load()
1154 intel_hda_update_irq(d); in intel_hda_post_load()
1159 .name = "intel-hda-stream",
1160 .version_id = 1,
1174 .name = "intel-hda",
1175 .version_id = 1,
1230 k->realize = intel_hda_realize; in intel_hda_class_init()
1231 k->exit = intel_hda_exit; in intel_hda_class_init()
1232 k->vendor_id = PCI_VENDOR_ID_INTEL; in intel_hda_class_init()
1233 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; in intel_hda_class_init()
1235 dc->vmsd = &vmstate_intel_hda; in intel_hda_class_init()
1244 k->device_id = 0x2668; in intel_hda_class_init_ich6()
1245 k->revision = 1; in intel_hda_class_init_ich6()
1246 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); in intel_hda_class_init_ich6()
1247 dc->desc = "Intel HD Audio Controller (ich6)"; in intel_hda_class_init_ich6()
1255 k->device_id = 0x293e; in intel_hda_class_init_ich9()
1256 k->revision = 3; in intel_hda_class_init_ich9()
1257 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); in intel_hda_class_init_ich9()
1258 dc->desc = "Intel HD Audio Controller (ich9)"; in intel_hda_class_init_ich9()
1274 .name = "intel-hda",
1280 .name = "ich9-intel-hda",
1288 k->realize = hda_codec_dev_realize; in hda_codec_device_class_init()
1289 k->unrealize = hda_codec_dev_unrealize; in hda_codec_device_class_init()
1290 set_bit(DEVICE_CATEGORY_SOUND, k->categories); in hda_codec_device_class_init()
1291 k->bus_type = TYPE_HDA_BUS; in hda_codec_device_class_init()
1306 * so '-soundhw hda' works.
1314 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); in intel_hda_and_codec_init()
1315 hdabus = QLIST_FIRST(&controller->child_bus); in intel_hda_and_codec_init()
1316 codec = qdev_new("hda-duplex"); in intel_hda_and_codec_init()