59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR        0x100
68 #define SLCR_LOCK_OFFSET        0x004
69 #define SLCR_UNLOCK_OFFSET      0x008
70 #define SLCR_ARM_PLL_OFFSET     0x100
72 #define SLCR_XILINX_UNLOCK_KEY  0xdf0d
73 #define SLCR_XILINX_LOCK_KEY    0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080  /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
85     0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
86     0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
87     0xe5801000 + (addr)
103         0xe3a004f8, /* mov r0, #0xf8000000 */  in zynq_write_board_setup()
105         SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),  in zynq_write_board_setup()
107         0xe12fff1e, /* bx lr */  in zynq_write_board_setup()
109     for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {  in zynq_write_board_setup()
128     sysbus_mmio_map(s, 0, base);  in gem_init()
129     sysbus_connect_irq(s, 0, irq);  in gem_init()
150     sysbus_mmio_map(busdev, 0, base_addr);  in zynq_init_spi_flashes()
152         sysbus_mmio_map(busdev, 1, 0xFC000000);  in zynq_init_spi_flashes()
154     sysbus_connect_irq(busdev, 0, irq);  in zynq_init_spi_flashes()
156     for (i = 0; i < num_busses; ++i) {  in zynq_init_spi_flashes()
163         for (j = 0; j < num_ss; ++j) {  in zynq_init_spi_flashes()
164             DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++);  in zynq_init_spi_flashes()
174             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);  in zynq_init_spi_flashes()
186     uint8_t mode = 0;  in zynq_set_boot_mode()
195         mode = 0;  in zynq_set_boot_mode()
220     for (n = 0; n < smp_cpus; n++) {  in zynq_init()
234     memory_region_add_subregion(address_space_mem, 0, machine->ram);  in zynq_init()
239     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);  in zynq_init()
241     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);  in zynq_init()
244     pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,  in zynq_init()
247                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,  in zynq_init()
248                           0);  in zynq_init()
262     sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);  in zynq_init()
268     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);  in zynq_init()
269     zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;  in zynq_init()
270     sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);  in zynq_init()
271     for (n = 0; n < smp_cpus; n++) {  in zynq_init()
280     for (n = 0; n < 64; n++) {  in zynq_init()
284     n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);  in zynq_init()
285     n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);  in zynq_init()
286     n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);  in zynq_init()
288     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);  in zynq_init()
289     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);  in zynq_init()
293     qdev_prop_set_chr(dev, "chardev", serial_hd(0));  in zynq_init()
297     sysbus_mmio_map(busdev, 0, 0xE0000000);  in zynq_init()
298     sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);  in zynq_init()
305     sysbus_mmio_map(busdev, 0, 0xE0001000);  in zynq_init()
306     sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);  in zynq_init()
308     sysbus_create_varargs("cadence_ttc", 0xF8001000,  in zynq_init()
310     sysbus_create_varargs("cadence_ttc", 0xF8002000,  in zynq_init()
313     gem_init(0xE000B000, pic[54 - IRQ_OFFSET]);  in zynq_init()
314     gem_init(0xE000C000, pic[77 - IRQ_OFFSET]);  in zynq_init()
316     for (n = 0; n < 2; n++) {  in zynq_init()
318         hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;  in zynq_init()
332         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);  in zynq_init()
333         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);  in zynq_init()
335         di = drive_get(IF_SD, 0, n);  in zynq_init()
345     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);  in zynq_init()
346     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);  in zynq_init()
365     sysbus_mmio_map(busdev, 0, 0xF8003000);  in zynq_init()
366     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */  in zynq_init()
367     for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */  in zynq_init()
374     sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);  in zynq_init()
375     sysbus_mmio_map(busdev, 0, 0xF8007000);  in zynq_init()
381     create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB);  in zynq_init()
382     create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB);  in zynq_init()
383     create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB);  in zynq_init()
384     create_unimplemented_device("zynq.can1", 0xE0009000, 4 * KiB);  in zynq_init()
385     create_unimplemented_device("zynq.gpio", 0xE000A000, 4 * KiB);  in zynq_init()
386     create_unimplemented_device("zynq.smcc", 0xE000E000, 4 * KiB);  in zynq_init()
389     create_unimplemented_device("zynq.dma_ns", 0xF8004000, 4 * KiB);  in zynq_init()
392     create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB);  in zynq_init()
395     create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB);  in zynq_init()
398     create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28);  in zynq_init()
399     create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28);  in zynq_init()
400     create_unimplemented_device("zynq.axi_hp2", 0xF800A000, 0x28);  in zynq_init()
401     create_unimplemented_device("zynq.axi_hp3", 0xF800B000, 0x28);  in zynq_init()
403     create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20);  in zynq_init()
406     create_unimplemented_device("zynq.etb", 0xF8801000, 4 * KiB);  in zynq_init()
409     create_unimplemented_device("zynq.cti_etb_tpiu", 0xF8802000, 4 * KiB);  in zynq_init()
412     create_unimplemented_device("zynq.tpiu", 0xF8803000, 4 * KiB);  in zynq_init()
415     create_unimplemented_device("zynq.funnel", 0xF8804000, 4 * KiB);  in zynq_init()
418     create_unimplemented_device("zynq.itm", 0xF8805000, 4 * KiB);  in zynq_init()
421     create_unimplemented_device("zynq.cti_ftm", 0xF8809000, 4 * KiB);  in zynq_init()
424     create_unimplemented_device("zynq.ftm", 0xF880B000, 4 * KiB);  in zynq_init()
427     create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB);  in zynq_init()
428     create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB);  in zynq_init()
431     create_unimplemented_device("zynq.cpu_cti0", 0xF8898000, 4 * KiB);  in zynq_init()
432     create_unimplemented_device("zynq.cpu_cti1", 0xF8899000, 4 * KiB);  in zynq_init()
435     create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB);  in zynq_init()
436     create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB);  in zynq_init()
439     create_unimplemented_device("zynq.trustZone", 0xF8900000, 0x20);  in zynq_init()
442     create_unimplemented_device("zynq.qos301_cpu", 0xF8946000, 0x130);  in zynq_init()
443     create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130);  in zynq_init()
444     create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130);  in zynq_init()
447     zynq_binfo.board_id = 0xd32;  in zynq_init()
448     zynq_binfo.loader_start = 0;  in zynq_init()
452     arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);  in zynq_init()