Lines Matching +full:migration +full:- +full:compat +full:- +full:common
2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/pci-bridge/pci_expander_bridge.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/core/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
64 #include "hw/qdev-properties.h"
74 #include "qapi/qapi-visit-common.h"
76 #include "standard-headers/linux/input.h"
80 #include "target/arm/cpu-qom.h"
84 #include "hw/mem/pc-dimm.h"
87 #include "hw/uefi/var-service-api.h"
88 #include "hw/virtio/virtio-md-pci.h"
89 #include "hw/virtio/virtio-iommu.h"
93 #include "qemu/guest-random.h"
96 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
102 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
107 compat_props_add(mc->compat_props, arm_virt_compat,
119 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
122 mc->alias = "virt"; \
202 /* Update the docs for highmem-mmio-size when changing this default */
217 * layout, depending on 'compact-highmem' property. With legacy layout, the
222 * Note that the highmem-mmio-size property will update the high PCIE MMIO size
242 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
243 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
244 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
245 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
258 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
259 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
270 CPUARMState *env = &cpu->env;
279 int nb_numa_nodes = ms->numa_state->num_nodes;
280 void *fdt = create_device_tree(&vms->fdt_size);
287 ms->fdt = fdt;
290 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
291 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
292 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
293 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
299 * - It avoids potential bugs where we forget to mark a DMA
300 * capable device as being dma-coherent
301 * - It avoids spurious warnings from the Linux kernel about
304 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
308 if (vms->dtb_randomness) {
312 if (vms->secure) {
313 qemu_fdt_add_subnode(fdt, "/secure-chosen");
314 if (vms->dtb_randomness) {
315 create_randomness(ms, "/secure-chosen");
326 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
327 qemu_fdt_add_subnode(fdt, "/apb-pclk");
328 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
329 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
330 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
331 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
333 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
335 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
346 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
350 qemu_fdt_add_subnode(fdt, "/distance-map");
351 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
352 "numa-distance-map-v1");
353 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
361 /* On real hardware these interrupts are level-triggered.
362 * On KVM they were edge-triggered before host kernel version 4.4,
363 * and level-triggered afterwards.
364 * On emulated QEMU they are level-triggered.
368 * pre-4.8 ignore the DT and leave the interrupt configured
375 * For backwards-compatibility, virt-2.8 and earlier will continue
376 * to say these are edge-triggered, but later machines will report
383 if (vms->gic_version == VIRT_GIC_VERSION_2) {
386 (1 << MACHINE(vms)->smp.cpus) - 1);
389 qemu_fdt_add_subnode(ms->fdt, "/timer");
392 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
393 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
394 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
395 compat, sizeof(compat));
397 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
398 "arm,armv7-timer");
400 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
401 if (vms->ns_el2_virt_timer_irq) {
402 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
414 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
432 int smp_cpus = ms->smp.cpus;
436 * On ARM v8 64-bit systems value should be set to 2,
439 * in the system, #address-cells can be set to 1, since
443 * Here we actually don't know whether our system is 32- or 64-bit one.
445 * at least one of them has Aff3 populated, we set #address-cells to 2.
456 qemu_fdt_add_subnode(ms->fdt, "/cpus");
457 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
458 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
460 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
465 qemu_fdt_add_subnode(ms->fdt, nodename);
466 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
467 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
468 armcpu->dtb_compatible);
470 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
471 qemu_fdt_setprop_string(ms->fdt, nodename,
472 "enable-method", "psci");
476 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
479 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
483 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
484 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
485 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
488 if (!vmc->no_cpu_topology) {
489 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
490 qemu_fdt_alloc_phandle(ms->fdt));
496 if (!vmc->no_cpu_topology) {
498 * Add vCPU topology description through fdt node cpu-map.
500 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
513 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
515 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
519 if (ms->smp.threads > 1) {
521 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
522 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
523 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
524 (cpu / ms->smp.threads) % ms->smp.cores,
525 cpu % ms->smp.threads);
528 "/cpus/cpu-map/socket%d/cluster%d/core%d",
529 cpu / (ms->smp.clusters * ms->smp.cores),
530 (cpu / ms->smp.cores) % ms->smp.clusters,
531 cpu % ms->smp.cores);
533 qemu_fdt_add_path(ms->fdt, map_path);
534 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
547 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
549 vms->memmap[VIRT_GIC_ITS].base);
550 qemu_fdt_add_subnode(ms->fdt, nodename);
551 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
552 "arm,gic-v3-its");
553 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
554 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
555 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
556 2, vms->memmap[VIRT_GIC_ITS].base,
557 2, vms->memmap[VIRT_GIC_ITS].size);
558 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
568 vms->memmap[VIRT_GIC_V2M].base);
569 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
570 qemu_fdt_add_subnode(ms->fdt, nodename);
571 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
572 "arm,gic-v2m-frame");
573 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
574 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
575 2, vms->memmap[VIRT_GIC_V2M].base,
576 2, vms->memmap[VIRT_GIC_V2M].size);
577 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
586 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
587 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
590 vms->memmap[VIRT_GIC_DIST].base);
591 qemu_fdt_add_subnode(ms->fdt, nodename);
592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
593 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
594 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
595 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
596 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
597 if (vms->gic_version != VIRT_GIC_VERSION_2) {
600 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
601 "arm,gic-v3");
603 qemu_fdt_setprop_cell(ms->fdt, nodename,
604 "#redistributor-regions", nb_redist_regions);
607 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
608 2, vms->memmap[VIRT_GIC_DIST].base,
609 2, vms->memmap[VIRT_GIC_DIST].size,
610 2, vms->memmap[VIRT_GIC_REDIST].base,
611 2, vms->memmap[VIRT_GIC_REDIST].size);
613 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
614 2, vms->memmap[VIRT_GIC_DIST].base,
615 2, vms->memmap[VIRT_GIC_DIST].size,
616 2, vms->memmap[VIRT_GIC_REDIST].base,
617 2, vms->memmap[VIRT_GIC_REDIST].size,
618 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
619 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
622 if (vms->virt) {
623 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
629 /* 'cortex-a15-gic' means 'GIC v2' */
630 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
631 "arm,cortex-a15-gic");
632 if (!vms->virt) {
633 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
634 2, vms->memmap[VIRT_GIC_DIST].base,
635 2, vms->memmap[VIRT_GIC_DIST].size,
636 2, vms->memmap[VIRT_GIC_CPU].base,
637 2, vms->memmap[VIRT_GIC_CPU].size);
639 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
640 2, vms->memmap[VIRT_GIC_DIST].base,
641 2, vms->memmap[VIRT_GIC_DIST].size,
642 2, vms->memmap[VIRT_GIC_CPU].base,
643 2, vms->memmap[VIRT_GIC_CPU].size,
644 2, vms->memmap[VIRT_GIC_HYP].base,
645 2, vms->memmap[VIRT_GIC_HYP].size,
646 2, vms->memmap[VIRT_GIC_VCPU].base,
647 2, vms->memmap[VIRT_GIC_VCPU].size);
648 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
655 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
665 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
670 if (vms->gic_version == VIRT_GIC_VERSION_2) {
673 (1 << MACHINE(vms)->smp.cpus) - 1);
676 qemu_fdt_add_subnode(ms->fdt, "/pmu");
677 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
678 const char compat[] = "arm,armv8-pmuv3";
679 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
680 compat, sizeof(compat));
681 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
692 int irq = vms->irqmap[VIRT_ACPI_GED];
696 if (ms->ram_slots) {
700 if (ms->nvdimms_state->is_enabled) {
705 qdev_prop_set_uint32(dev, "ged-event", event);
706 object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort);
710 sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].base);
712 vms->memmap[VIRT_PCDIMM_ACPI].base);
721 vms->memmap[VIRT_ACPI_PCIHP].base);
725 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq));
734 assert(vms->its);
735 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) {
745 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
748 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
751 vms->msi_controller = VIRT_MSI_CTRL_ITS;
757 int irq = vms->irqmap[VIRT_GIC_V2M];
760 dev = qdev_new("arm-gicv2m");
761 qdev_prop_set_uint32(dev, "base-spi", irq);
762 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
764 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
768 qdev_get_gpio_in(vms->gic, irq + i));
772 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
786 (vms->gic_version != VIRT_GIC_VERSION_2);
796 unsigned int smp_cpus = ms->smp.cpus;
800 if (vms->gic_version == VIRT_GIC_VERSION_2) {
806 switch (vms->gic_version) {
820 if (kvm_enabled() && vms->virt &&
822 error_report("KVM EL2 is only supported with in-kernel GICv3");
826 vms->gic = qdev_new(gictype);
827 qdev_prop_set_uint32(vms->gic, "revision", revision);
828 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
829 /* Note that the num-irq property counts both internal and external
832 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
834 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
837 if (vms->gic_version != VIRT_GIC_VERSION_2) {
851 MIN(smp_cpus - redist0_count, redist1_capacity));
853 qdev_prop_set_array(vms->gic, "redist-region-count",
857 if (vms->tcg_its) {
858 object_property_set_link(OBJECT(vms->gic), "sysmem",
860 qdev_prop_set_bit(vms->gic, "has-lpi", true);
862 } else if (vms->virt) {
863 qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id",
868 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
869 vms->virt);
874 qdev_prop_set_bit(vms->gic, "has-nmi", true);
877 gicbusdev = SYS_BUS_DEVICE(vms->gic);
879 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
880 if (vms->gic_version != VIRT_GIC_VERSION_2) {
881 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
884 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
887 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
888 if (vms->virt) {
889 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
890 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
917 qdev_get_gpio_in(vms->gic,
921 if (vms->gic_version != VIRT_GIC_VERSION_2) {
922 qemu_irq irq = qdev_get_gpio_in(vms->gic,
924 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
926 } else if (vms->virt) {
927 qemu_irq irq = qdev_get_gpio_in(vms->gic,
932 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
933 qdev_get_gpio_in(vms->gic, intidbase
944 if (vms->gic_version != VIRT_GIC_VERSION_2) {
954 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
956 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
965 hwaddr base = vms->memmap[uart].base;
966 hwaddr size = vms->memmap[uart].size;
967 int irq = vms->irqmap[uart];
968 const char compat[] = "arm,pl011\0arm,primecell";
978 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
981 qemu_fdt_add_subnode(ms->fdt, nodename);
983 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
984 compat, sizeof(compat));
985 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
987 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
990 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
991 vms->clock_phandle, vms->clock_phandle);
992 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
996 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
997 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
999 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
1003 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1004 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1006 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
1016 hwaddr base = vms->memmap[VIRT_RTC].base;
1017 hwaddr size = vms->memmap[VIRT_RTC].size;
1018 int irq = vms->irqmap[VIRT_RTC];
1019 const char compat[] = "arm,pl031\0arm,primecell";
1022 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
1025 qemu_fdt_add_subnode(ms->fdt, nodename);
1026 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1027 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1029 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1032 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1033 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1042 if (s->acpi_dev) {
1043 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1053 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1057 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1058 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1060 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1061 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1063 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1065 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1077 /* gpio-pwr */
1078 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1080 /* connect secure pl061 to gpio-pwr */
1086 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1087 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1088 "gpio-poweroff");
1089 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1091 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1092 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1095 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1096 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1097 "gpio-restart");
1098 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1100 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1101 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1110 hwaddr base = vms->memmap[gpio].base;
1111 hwaddr size = vms->memmap[gpio].size;
1112 int irq = vms->irqmap[gpio];
1113 const char compat[] = "arm,pl061\0arm,primecell";
1124 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1126 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1128 qemu_fdt_add_subnode(ms->fdt, nodename);
1129 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1131 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1132 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1133 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1134 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1137 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1138 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1139 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1143 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1144 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1150 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1152 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1159 hwaddr size = vms->memmap[VIRT_MMIO].size;
1164 * create a list of virtio-mmio buses with decreasing base addresses.
1166 * When a -device option is processed from the command line,
1167 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1168 * order. The upshot is that -device options in increasing command line
1169 * order are mapped to virtio-mmio buses with decreasing base addresses.
1173 * the first -device on the command line. (The end-to-end order is a
1175 * guest kernel's name-to-address assignment strategy.)
1190 int irq = vms->irqmap[VIRT_MMIO] + i;
1191 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1193 sysbus_create_simple("virtio-mmio", base,
1194 qdev_get_gpio_in(vms->gic, irq));
1204 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1206 int irq = vms->irqmap[VIRT_MMIO] + i;
1207 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1210 qemu_fdt_add_subnode(ms->fdt, nodename);
1211 qemu_fdt_setprop_string(ms->fdt, nodename,
1213 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1215 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1218 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1235 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1237 qdev_prop_set_uint8(dev, "device-width", 2);
1238 qdev_prop_set_bit(dev, "big-endian", false);
1252 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1253 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1264 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1284 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1285 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1287 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1289 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1297 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1298 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1305 qemu_fdt_add_subnode(ms->fdt, nodename);
1306 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1307 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1310 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1318 qemu_fdt_add_subnode(ms->fdt, nodename);
1319 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1320 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1322 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1323 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1324 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1328 qemu_fdt_add_subnode(ms->fdt, nodename);
1329 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1330 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1332 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1345 /* Map legacy -drive if=pflash to machine properties */
1346 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1347 pflash_cfi01_legacy_drive(vms->flash[i],
1353 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1355 bios_name = MACHINE(vms)->firmware;
1363 "specified with -bios or with -drive if=pflash... "
1368 /* Fall back to -bios */
1375 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1390 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1391 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1396 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1398 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1399 qemu_fdt_add_subnode(ms->fdt, nodename);
1400 qemu_fdt_setprop_string(ms->fdt, nodename,
1401 "compatible", "qemu,fw-cfg-mmio");
1402 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1404 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1437 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1440 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1451 const char compat[] = "arm,smmu-v3";
1452 int irq = vms->irqmap[VIRT_SMMU];
1454 hwaddr base = vms->memmap[VIRT_SMMU].base;
1455 hwaddr size = vms->memmap[VIRT_SMMU].size;
1456 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1460 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1466 if (!vmc->no_nested_smmu) {
1469 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1475 qdev_get_gpio_in(vms->gic, irq + i));
1479 qemu_fdt_add_subnode(ms->fdt, node);
1480 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1481 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1483 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1489 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1492 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1494 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1496 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1502 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1503 uint16_t bdf = vms->virtio_iommu_bdf;
1507 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1509 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1511 qemu_fdt_add_subnode(ms->fdt, node);
1512 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1513 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1517 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1518 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1521 if (!vms->default_bus_bypass_iommu) {
1522 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1523 0x0, vms->iommu_phandle, 0x0, bdf,
1524 bdf + 1, vms->iommu_phandle, bdf + 1,
1525 0xffff - bdf);
1531 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1532 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1533 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1534 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1535 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1536 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1540 int irq = vms->irqmap[VIRT_PCIE];
1555 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1556 base_ecam = vms->memmap[ecam_id].base;
1557 size_ecam = vms->memmap[ecam_id].size;
1562 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1573 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1577 if (vms->highmem_mmio) {
1581 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1592 qdev_get_gpio_in(vms->gic, irq + i));
1597 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1598 vms->bus = pci->bus;
1599 if (vms->bus) {
1600 pci_init_nic_devices(pci->bus, mc->default_nic);
1603 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1604 qemu_fdt_add_subnode(ms->fdt, nodename);
1605 qemu_fdt_setprop_string(ms->fdt, nodename,
1606 "compatible", "pci-host-ecam-generic");
1607 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1608 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1609 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1610 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1611 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1612 nr_pcie_buses - 1);
1613 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1615 if (vms->msi_phandle) {
1616 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1617 0, vms->msi_phandle, 0, 0x10000);
1620 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1623 if (vms->highmem_mmio) {
1624 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1633 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1640 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1641 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1643 if (vms->iommu) {
1644 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1646 switch (vms->iommu) {
1648 create_smmu(vms, vms->bus);
1649 if (!vms->default_bus_bypass_iommu) {
1650 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1651 0x0, vms->iommu_phandle, 0x0, 0x10000);
1663 MemoryRegion *mr = &vms->cxl_devices_state.host_mr;
1666 vms->memmap[VIRT_CXL_HOST].size);
1667 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr);
1668 vms->highmem_cxl = true;
1679 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1681 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1683 vms->platform_bus_dev = dev;
1687 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1688 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1692 vms->memmap[VIRT_PLATFORM_BUS].base,
1712 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1713 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1716 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1721 qemu_fdt_add_subnode(ms->fdt, nodename);
1722 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1723 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1724 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1725 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1728 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1741 *fdt_size = board->fdt_size;
1742 return ms->fdt;
1758 smbios_set_defaults("QEMU", product, mc->name);
1761 mem_array.address = vms->memmap[VIRT_MEM].base;
1762 mem_array.length = ms->ram_size;
1770 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1772 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1784 struct arm_boot_info *info = &vms->bootinfo;
1787 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state,
1790 if (vms->cxl_devices_state.is_enabled) {
1800 if (info->dtb_filename == NULL) {
1801 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1802 vms->memmap[VIRT_PLATFORM_BUS].base,
1803 vms->memmap[VIRT_PLATFORM_BUS].size,
1804 vms->irqmap[VIRT_PLATFORM_BUS]);
1806 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
1810 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,
1822 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)
1825 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1838 &vms->highmem_redists,
1839 &vms->highmem_cxl,
1840 &vms->highmem_ecam,
1841 &vms->highmem_mmio,
1844 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1846 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1848 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1863 vms->memmap[i].base = region_base;
1864 vms->memmap[i].size = region_size;
1876 if (vms->highmem_compact && !*region_enabled) {
1882 vms->highest_gpa = base - 1;
1893 vms->memmap = extended_memmap;
1896 vms->memmap[i] = base_memmap[i];
1899 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1901 ms->ram_slots);
1909 if (!vms->highmem) {
1921 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1922 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1928 pa_bits, memtop - BIT_ULL(pa_bits));
1935 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1936 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1940 vms->highest_gpa = memtop - 1;
1947 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1,
1949 BIT_ULL(pa_bits)) - 1;
1961 error_report("gic-version=host requires KVM");
1965 /* For KVM, gic-version=host means gic-version=max */
1984 * the end-user requested more than 8 VCPUs we now default
2031 * finalize_gic_version - Determines the final gic_version
2032 * according to the gic-version property
2039 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
2060 accel_name = "KVM with kernel-irqchip=off";
2063 if (module_object_class_by_name("arm-gicv3")) {
2065 if (vms->virt) {
2079 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2090 int max_cpus = MACHINE(vms)->smp.max_cpus;
2097 "kvm-steal-time", NULL);
2100 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2101 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2121 if (!aarch64 && vms->virt) {
2128 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2136 + cpu->cpu_index
2141 if (aarch64 && vms->highmem) {
2142 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2168 bool has_ged = !vmc->no_ged;
2169 unsigned int smp_cpus = machine->smp.cpus;
2170 unsigned int max_cpus = machine->smp.max_cpus;
2172 possible_cpus = mc->possible_cpu_arch_ids(machine);
2179 if (!vms->memmap) {
2189 cpuobj = object_new(possible_cpus->cpus[0].type);
2204 if (vms->secure) {
2208 * containing the system memory at low priority; any secure-only
2212 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2214 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2230 if (vms->secure && firmware_loaded) {
2231 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2232 } else if (vms->virt) {
2233 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2235 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2243 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2247 if (vms->highmem_redists) {
2254 "supported by machine 'mach-virt' (%d)",
2256 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2257 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2263 if (vms->secure && !tcg_enabled() && !qtest_enabled()) {
2264 error_report("mach-virt: %s does not support providing "
2270 if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) {
2271 error_report("mach-virt: host kernel KVM does not support providing "
2276 if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled()) {
2277 error_report("mach-virt: %s does not support providing "
2283 if (vms->mte && hvf_enabled()) {
2284 error_report("mach-virt: %s does not support providing "
2292 assert(possible_cpus->len == max_cpus);
2293 for (n = 0; n < possible_cpus->len; n++) {
2301 cpuobj = object_new(possible_cpus->cpus[n].type);
2302 object_property_set_int(cpuobj, "mp-affinity",
2303 possible_cpus->cpus[n].arch_id, NULL);
2306 cs->cpu_index = n;
2308 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2313 if (!vms->secure) {
2317 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2321 if (vmc->kvm_no_adjvtime &&
2322 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2323 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2326 if (vmc->no_kvm_steal_time &&
2327 object_property_find(cpuobj, "kvm-steal-time")) {
2328 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2331 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2335 if (object_property_find(cpuobj, "reset-cbar")) {
2336 object_property_set_int(cpuobj, "reset-cbar",
2337 vms->memmap[VIRT_CPUPERIPHS].base,
2343 if (vms->secure) {
2344 object_property_set_link(cpuobj, "secure-memory",
2348 if (vms->mte) {
2356 if (!object_property_find(cpuobj, "tag-memory")) {
2364 "tag-memory", UINT64_MAX / 32);
2366 if (vms->secure) {
2369 "secure-tag-memory",
2372 /* As with ram, secure-tag takes precedence over tag. */
2374 0, tag_sysmem, -1);
2378 object_property_set_link(cpuobj, "tag-memory",
2380 if (vms->secure) {
2381 object_property_set_link(cpuobj, "secure-tag-memory",
2402 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2403 !vmc->no_ns_el2_virt_timer_irq;
2408 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2409 machine->ram);
2424 * if a backend is configured explicitly via '-serial <backend>'.
2434 * aliases node information and /chosen/stdout-path regardless of
2437 * For similar back-compatibility reasons, if UART1 is the secure UART
2441 if (!vms->secure) {
2445 vms->second_ns_uart_present = true;
2450 if (vms->secure) {
2454 if (vms->secure) {
2459 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2460 machine->ram_size, "mach-virt.tag");
2463 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2471 vms->acpi_dev = create_acpi_ged(vms);
2476 if (vms->secure && !vmc->no_secure_gpio) {
2481 vms->powerdown_notifier.notify = virt_powerdown_req;
2482 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2490 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2491 rom_set_fw(vms->fw_cfg);
2495 if (machine->nvdimms_state->is_enabled) {
2498 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2502 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2504 vms->fw_cfg, OBJECT(vms));
2507 vms->bootinfo.ram_size = machine->ram_size;
2508 vms->bootinfo.board_id = -1;
2509 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2510 vms->bootinfo.get_dtb = machvirt_dtb;
2511 vms->bootinfo.skip_dtb_autoload = true;
2512 vms->bootinfo.firmware_loaded = firmware_loaded;
2513 vms->bootinfo.psci_conduit = vms->psci_conduit;
2514 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2516 vms->machine_done.notify = virt_machine_done;
2517 qemu_add_machine_init_done_notifier(&vms->machine_done);
2524 return vms->secure;
2531 vms->secure = value;
2538 return vms->virt;
2545 vms->virt = value;
2552 return vms->highmem;
2559 vms->highmem = value;
2566 return vms->highmem_compact;
2573 vms->highmem_compact = value;
2580 return vms->highmem_redists;
2587 vms->highmem_redists = value;
2594 return vms->highmem_ecam;
2601 vms->highmem_ecam = value;
2608 return vms->highmem_mmio;
2615 vms->highmem_mmio = value;
2638 error_setg(errp, "highmem-mmio-size is not a power of 2");
2644 error_setg(errp, "highmem-mmio-size cannot be set to a lower value "
2657 return vms->its;
2664 vms->its = value;
2671 return vms->dtb_randomness;
2678 vms->dtb_randomness = value;
2685 return g_strdup(vms->oem_id);
2695 "User specified oem-id value is bigger than 6 bytes in size");
2699 strncpy(vms->oem_id, value, 6);
2706 return g_strdup(vms->oem_table_id);
2717 "User specified oem-table-id value is bigger than 8 bytes in size");
2720 strncpy(vms->oem_table_id, value, 8);
2726 if (vms->acpi == ON_OFF_AUTO_OFF) {
2736 OnOffAuto acpi = vms->acpi;
2746 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2753 return vms->ras;
2760 vms->ras = value;
2767 return vms->mte;
2774 vms->mte = value;
2782 switch (vms->gic_version) {
2801 vms->gic_version = VIRT_GIC_VERSION_4;
2803 vms->gic_version = VIRT_GIC_VERSION_3;
2805 vms->gic_version = VIRT_GIC_VERSION_2;
2807 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2809 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2811 error_setg(errp, "Invalid gic-version value");
2820 switch (vms->iommu) {
2835 vms->iommu = VIRT_IOMMU_SMMUV3;
2837 vms->iommu = VIRT_IOMMU_NONE;
2848 return vms->default_bus_bypass_iommu;
2856 vms->default_bus_bypass_iommu = value;
2863 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2865 assert(cpu_index < possible_cpus->len);
2866 return possible_cpus->cpus[cpu_index].props;
2871 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2873 return socket_id % ms->numa_state->num_nodes;
2879 unsigned int max_cpus = ms->smp.max_cpus;
2883 if (ms->possible_cpus) {
2884 assert(ms->possible_cpus->len == max_cpus);
2885 return ms->possible_cpus;
2888 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2890 ms->possible_cpus->len = max_cpus;
2891 for (n = 0; n < ms->possible_cpus->len; n++) {
2892 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2893 ms->possible_cpus->cpus[n].arch_id =
2896 assert(!mc->smp_props.dies_supported);
2897 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2898 ms->possible_cpus->cpus[n].props.socket_id =
2899 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2900 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2901 ms->possible_cpus->cpus[n].props.cluster_id =
2902 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2903 ms->possible_cpus->cpus[n].props.has_core_id = true;
2904 ms->possible_cpus->cpus[n].props.core_id =
2905 (n / ms->smp.threads) % ms->smp.cores;
2906 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2907 ms->possible_cpus->cpus[n].props.thread_id =
2908 n % ms->smp.threads;
2910 return ms->possible_cpus;
2920 if (!vms->acpi_dev) {
2922 "memory hotplug is not enabled: missing acpi-ged device");
2926 if (vms->mte) {
2931 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2932 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2949 nvdimm_plug(ms->nvdimms_state);
2952 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2970 if (vms->iommu != VIRT_IOMMU_NONE) {
2975 switch (vms->msi_controller) {
2982 base_memmap[VIRT_GIC_ITS].size - 1;
2987 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2996 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
3006 if (vms->platform_bus_dev) {
3010 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
3024 vms->iommu = VIRT_IOMMU_VIRTIO;
3025 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
3035 if (!vms->acpi_dev) {
3037 "memory hotplug is not enabled: missing acpi-ged device");
3046 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
3056 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
3110 * for arm64 kvm_type [7-0] encodes the requested number of bits
3124 requested_pa_size = 64 - clz64(vms->highest_gpa);
3134 error_report("-m and ,maxmem option values "
3138 return -1;
3158 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3171 error_report("-m and ,maxmem option values "
3175 return -1;
3187 ARM_CPU_TYPE_NAME("cortex-a7"),
3188 ARM_CPU_TYPE_NAME("cortex-a15"),
3190 ARM_CPU_TYPE_NAME("cortex-a35"),
3191 ARM_CPU_TYPE_NAME("cortex-a55"),
3192 ARM_CPU_TYPE_NAME("cortex-a72"),
3193 ARM_CPU_TYPE_NAME("cortex-a76"),
3194 ARM_CPU_TYPE_NAME("cortex-a710"),
3196 ARM_CPU_TYPE_NAME("neoverse-n1"),
3197 ARM_CPU_TYPE_NAME("neoverse-v1"),
3198 ARM_CPU_TYPE_NAME("neoverse-n2"),
3202 ARM_CPU_TYPE_NAME("cortex-a53"),
3203 ARM_CPU_TYPE_NAME("cortex-a57"),
3212 mc->init = machvirt_init;
3217 mc->max_cpus = 512;
3226 mc->block_default_type = IF_VIRTIO;
3227 mc->no_cdrom = 1;
3228 mc->pci_allow_0_address = true;
3229 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3230 mc->minimum_page_bits = 12;
3231 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3232 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3234 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3236 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3238 mc->valid_cpu_types = valid_cpu_types;
3239 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3240 mc->kvm_type = virt_kvm_type;
3241 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3242 assert(!mc->get_hotplug_handler);
3243 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3244 hc->pre_plug = virt_machine_device_pre_plug_cb;
3245 hc->plug = virt_machine_device_plug_cb;
3246 hc->unplug_request = virt_machine_device_unplug_request_cb;
3247 hc->unplug = virt_machine_device_unplug_cb;
3248 mc->nvdimm_supported = true;
3249 mc->smp_props.clusters_supported = true;
3250 mc->auto_enable_numa_with_memhp = true;
3251 mc->auto_enable_numa_with_memdev = true;
3253 mc->cpu_cluster_has_numa_boundary = true;
3254 mc->default_ram_id = "mach-virt.ram";
3255 mc->default_nic = "virtio-net-pci";
3281 object_class_property_add_bool(oc, "compact-highmem",
3284 object_class_property_set_description(oc, "compact-highmem",
3288 object_class_property_add_bool(oc, "highmem-redists",
3291 object_class_property_set_description(oc, "highmem-redists",
3296 object_class_property_add_bool(oc, "highmem-ecam",
3299 object_class_property_set_description(oc, "highmem-ecam",
3303 object_class_property_add_bool(oc, "highmem-mmio",
3306 object_class_property_set_description(oc, "highmem-mmio",
3310 object_class_property_add(oc, "highmem-mmio-size", "size",
3314 object_class_property_set_description(oc, "highmem-mmio-size",
3318 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3320 object_class_property_set_description(oc, "gic-version",
3329 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3332 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3354 object_class_property_add_bool(oc, "dtb-randomness",
3357 object_class_property_set_description(oc, "dtb-randomness",
3359 "non-deterministic dtb nodes to guest");
3361 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3364 object_class_property_set_description(oc, "dtb-kaslr-seed",
3365 "Deprecated synonym of dtb-randomness");
3367 object_class_property_add_str(oc, "x-oem-id",
3370 object_class_property_set_description(oc, "x-oem-id",
3376 object_class_property_add_str(oc, "x-oem-table-id",
3379 object_class_property_set_description(oc, "x-oem-table-id",
3395 vms->secure = false;
3398 vms->virt = false;
3401 vms->highmem = true;
3402 vms->highmem_compact = !vmc->no_highmem_compact;
3403 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3405 vms->highmem_ecam = true;
3406 vms->highmem_mmio = true;
3407 vms->highmem_redists = true;
3410 vms->its = true;
3412 vms->tcg_its = !vmc->no_tcg_its;
3415 vms->iommu = VIRT_IOMMU_NONE;
3418 vms->default_bus_bypass_iommu = false;
3421 vms->ras = false;
3424 vms->mte = false;
3426 /* Supply kaslr-seed and rng-seed by default */
3427 vms->dtb_randomness = true;
3429 vms->irqmap = a15irqmap;
3433 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3434 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3435 cxl_machine_init(obj, &vms->cxl_devices_state);
3466 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len);
3473 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len);
3482 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3483 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3484 vmc->no_nested_smmu = true;
3491 mc->smbios_memory_device_size = 16 * GiB;
3492 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3501 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3507 vmc->no_ns_el2_virt_timer_irq = true;
3514 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3521 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3528 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3537 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3539 vmc->no_highmem_compact = true;
3546 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3555 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3556 vmc->no_tcg_lpa2 = true;
3565 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3566 mc->smp_props.prefer_sockets = true;
3567 vmc->no_cpu_topology = true;
3570 vmc->no_tcg_its = true;
3577 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3586 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3587 vmc->no_secure_gpio = true;
3596 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3597 vmc->no_kvm_steal_time = true;
3606 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3607 mc->numa_mem_supported = true;
3608 vmc->acpi_expose_flash = true;
3609 mc->auto_enable_numa_with_memdev = false;
3618 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3619 vmc->kvm_no_adjvtime = true;
3628 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3629 vmc->no_ged = true;
3630 mc->auto_enable_numa_with_memhp = false;