Lines Matching +full:migration +full:- +full:compat +full:- +full:aarch64
2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
56 #include "qemu/error-report.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
72 #include "qapi/qapi-visit-common.h"
74 #include "standard-headers/linux/input.h"
77 #include "target/arm/cpu-qom.h"
81 #include "hw/mem/pc-dimm.h"
84 #include "hw/virtio/virtio-md-pci.h"
85 #include "hw/virtio/virtio-iommu.h"
87 #include "qemu/guest-random.h"
90 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
96 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
101 compat_props_add(mc->compat_props, arm_virt_compat,
113 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
116 mc->alias = "virt"; \
206 * layout, depending on 'compact-highmem' property. With legacy layout, the
226 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
227 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
228 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
229 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
242 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
243 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
254 CPUARMState *env = &cpu->env;
263 int nb_numa_nodes = ms->numa_state->num_nodes;
264 void *fdt = create_device_tree(&vms->fdt_size);
271 ms->fdt = fdt;
274 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
275 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
276 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
277 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
283 * - It avoids potential bugs where we forget to mark a DMA
284 * capable device as being dma-coherent
285 * - It avoids spurious warnings from the Linux kernel about
288 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
292 if (vms->dtb_randomness) {
296 if (vms->secure) {
297 qemu_fdt_add_subnode(fdt, "/secure-chosen");
298 if (vms->dtb_randomness) {
299 create_randomness(ms, "/secure-chosen");
310 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
311 qemu_fdt_add_subnode(fdt, "/apb-pclk");
312 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
313 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
314 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
315 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
317 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
319 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
330 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
334 qemu_fdt_add_subnode(fdt, "/distance-map");
335 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
336 "numa-distance-map-v1");
337 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
345 /* On real hardware these interrupts are level-triggered.
346 * On KVM they were edge-triggered before host kernel version 4.4,
347 * and level-triggered afterwards.
348 * On emulated QEMU they are level-triggered.
352 * pre-4.8 ignore the DT and leave the interrupt configured
359 * For backwards-compatibility, virt-2.8 and earlier will continue
360 * to say these are edge-triggered, but later machines will report
368 if (vmc->claim_edge_triggered_timers) {
372 if (vms->gic_version == VIRT_GIC_VERSION_2) {
375 (1 << MACHINE(vms)->smp.cpus) - 1);
378 qemu_fdt_add_subnode(ms->fdt, "/timer");
381 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
382 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
383 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
384 compat, sizeof(compat));
386 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
387 "arm,armv7-timer");
389 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
390 if (vms->ns_el2_virt_timer_irq) {
391 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
403 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
421 int smp_cpus = ms->smp.cpus;
425 * On ARM v8 64-bit systems value should be set to 2,
428 * in the system, #address-cells can be set to 1, since
432 * Here we actually don't know whether our system is 32- or 64-bit one.
434 * at least one of them has Aff3 populated, we set #address-cells to 2.
445 qemu_fdt_add_subnode(ms->fdt, "/cpus");
446 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
447 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
449 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
454 qemu_fdt_add_subnode(ms->fdt, nodename);
455 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
456 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
457 armcpu->dtb_compatible);
459 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
460 qemu_fdt_setprop_string(ms->fdt, nodename,
461 "enable-method", "psci");
465 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
468 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
472 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
473 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
474 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
477 if (!vmc->no_cpu_topology) {
478 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
479 qemu_fdt_alloc_phandle(ms->fdt));
485 if (!vmc->no_cpu_topology) {
487 * Add vCPU topology description through fdt node cpu-map.
489 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
502 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
504 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
508 if (ms->smp.threads > 1) {
510 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
511 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
512 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
513 (cpu / ms->smp.threads) % ms->smp.cores,
514 cpu % ms->smp.threads);
517 "/cpus/cpu-map/socket%d/cluster%d/core%d",
518 cpu / (ms->smp.clusters * ms->smp.cores),
519 (cpu / ms->smp.cores) % ms->smp.clusters,
520 cpu % ms->smp.cores);
522 qemu_fdt_add_path(ms->fdt, map_path);
523 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
536 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
538 vms->memmap[VIRT_GIC_ITS].base);
539 qemu_fdt_add_subnode(ms->fdt, nodename);
540 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
541 "arm,gic-v3-its");
542 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
544 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
545 2, vms->memmap[VIRT_GIC_ITS].base,
546 2, vms->memmap[VIRT_GIC_ITS].size);
547 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
557 vms->memmap[VIRT_GIC_V2M].base);
558 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
559 qemu_fdt_add_subnode(ms->fdt, nodename);
560 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
561 "arm,gic-v2m-frame");
562 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
563 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
564 2, vms->memmap[VIRT_GIC_V2M].base,
565 2, vms->memmap[VIRT_GIC_V2M].size);
566 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
575 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
576 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
579 vms->memmap[VIRT_GIC_DIST].base);
580 qemu_fdt_add_subnode(ms->fdt, nodename);
581 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
582 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
583 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
584 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
585 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
586 if (vms->gic_version != VIRT_GIC_VERSION_2) {
589 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
590 "arm,gic-v3");
592 qemu_fdt_setprop_cell(ms->fdt, nodename,
593 "#redistributor-regions", nb_redist_regions);
596 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
597 2, vms->memmap[VIRT_GIC_DIST].base,
598 2, vms->memmap[VIRT_GIC_DIST].size,
599 2, vms->memmap[VIRT_GIC_REDIST].base,
600 2, vms->memmap[VIRT_GIC_REDIST].size);
602 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
603 2, vms->memmap[VIRT_GIC_DIST].base,
604 2, vms->memmap[VIRT_GIC_DIST].size,
605 2, vms->memmap[VIRT_GIC_REDIST].base,
606 2, vms->memmap[VIRT_GIC_REDIST].size,
607 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
608 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
611 if (vms->virt) {
612 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
618 /* 'cortex-a15-gic' means 'GIC v2' */
619 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
620 "arm,cortex-a15-gic");
621 if (!vms->virt) {
622 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
623 2, vms->memmap[VIRT_GIC_DIST].base,
624 2, vms->memmap[VIRT_GIC_DIST].size,
625 2, vms->memmap[VIRT_GIC_CPU].base,
626 2, vms->memmap[VIRT_GIC_CPU].size);
628 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
629 2, vms->memmap[VIRT_GIC_DIST].base,
630 2, vms->memmap[VIRT_GIC_DIST].size,
631 2, vms->memmap[VIRT_GIC_CPU].base,
632 2, vms->memmap[VIRT_GIC_CPU].size,
633 2, vms->memmap[VIRT_GIC_HYP].base,
634 2, vms->memmap[VIRT_GIC_HYP].size,
635 2, vms->memmap[VIRT_GIC_VCPU].base,
636 2, vms->memmap[VIRT_GIC_VCPU].size);
637 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
644 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
654 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
659 if (vms->gic_version == VIRT_GIC_VERSION_2) {
662 (1 << MACHINE(vms)->smp.cpus) - 1);
665 qemu_fdt_add_subnode(ms->fdt, "/pmu");
666 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
667 const char compat[] = "arm,armv8-pmuv3";
668 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
669 compat, sizeof(compat));
670 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
680 int irq = vms->irqmap[VIRT_ACPI_GED];
683 if (ms->ram_slots) {
687 if (ms->nvdimms_state->is_enabled) {
692 qdev_prop_set_uint32(dev, "ged-event", event);
695 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
696 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
697 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
707 if (!strcmp(itsclass, "arm-gicv3-its")) {
708 if (!vms->tcg_its) {
720 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
723 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
726 vms->msi_controller = VIRT_MSI_CTRL_ITS;
732 int irq = vms->irqmap[VIRT_GIC_V2M];
735 dev = qdev_new("arm-gicv2m");
736 qdev_prop_set_uint32(dev, "base-spi", irq);
737 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
739 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
743 qdev_get_gpio_in(vms->gic, irq + i));
747 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
761 (vms->gic_version != VIRT_GIC_VERSION_2);
771 unsigned int smp_cpus = ms->smp.cpus;
775 if (vms->gic_version == VIRT_GIC_VERSION_2) {
781 switch (vms->gic_version) {
794 vms->gic = qdev_new(gictype);
795 qdev_prop_set_uint32(vms->gic, "revision", revision);
796 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
797 /* Note that the num-irq property counts both internal and external
800 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
802 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
805 if (vms->gic_version != VIRT_GIC_VERSION_2) {
819 MIN(smp_cpus - redist0_count, redist1_capacity));
821 qdev_prop_set_array(vms->gic, "redist-region-count",
825 if (vms->tcg_its) {
826 object_property_set_link(OBJECT(vms->gic), "sysmem",
828 qdev_prop_set_bit(vms->gic, "has-lpi", true);
833 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
834 vms->virt);
839 qdev_prop_set_bit(vms->gic, "has-nmi", true);
842 gicbusdev = SYS_BUS_DEVICE(vms->gic);
844 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
845 if (vms->gic_version != VIRT_GIC_VERSION_2) {
846 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
849 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
852 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
853 if (vms->virt) {
854 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
855 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
882 qdev_get_gpio_in(vms->gic,
886 if (vms->gic_version != VIRT_GIC_VERSION_2) {
887 qemu_irq irq = qdev_get_gpio_in(vms->gic,
889 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
891 } else if (vms->virt) {
892 qemu_irq irq = qdev_get_gpio_in(vms->gic,
897 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
898 qdev_get_gpio_in(vms->gic, intidbase
909 if (vms->gic_version != VIRT_GIC_VERSION_2) {
919 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
921 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
930 hwaddr base = vms->memmap[uart].base;
931 hwaddr size = vms->memmap[uart].size;
932 int irq = vms->irqmap[uart];
933 const char compat[] = "arm,pl011\0arm,primecell";
943 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
946 qemu_fdt_add_subnode(ms->fdt, nodename);
948 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
949 compat, sizeof(compat));
950 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
952 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
955 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
956 vms->clock_phandle, vms->clock_phandle);
957 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
961 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
962 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
964 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
968 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
969 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
971 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
981 hwaddr base = vms->memmap[VIRT_RTC].base;
982 hwaddr size = vms->memmap[VIRT_RTC].size;
983 int irq = vms->irqmap[VIRT_RTC];
984 const char compat[] = "arm,pl031\0arm,primecell";
987 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
990 qemu_fdt_add_subnode(ms->fdt, nodename);
991 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
992 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
994 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
997 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
998 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1007 if (s->acpi_dev) {
1008 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1018 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1022 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1023 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1025 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1026 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1028 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1030 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1042 /* gpio-pwr */
1043 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1045 /* connect secure pl061 to gpio-pwr */
1051 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1052 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1053 "gpio-poweroff");
1054 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1056 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1057 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1060 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1061 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1062 "gpio-restart");
1063 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1065 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1066 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1075 hwaddr base = vms->memmap[gpio].base;
1076 hwaddr size = vms->memmap[gpio].size;
1077 int irq = vms->irqmap[gpio];
1078 const char compat[] = "arm,pl061\0arm,primecell";
1089 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1091 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1093 qemu_fdt_add_subnode(ms->fdt, nodename);
1094 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1096 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1097 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1098 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1099 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1102 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1103 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1104 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1108 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1109 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1115 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1117 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1124 hwaddr size = vms->memmap[VIRT_MMIO].size;
1129 * create a list of virtio-mmio buses with decreasing base addresses.
1131 * When a -device option is processed from the command line,
1132 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1133 * order. The upshot is that -device options in increasing command line
1134 * order are mapped to virtio-mmio buses with decreasing base addresses.
1138 * the first -device on the command line. (The end-to-end order is a
1140 * guest kernel's name-to-address assignment strategy.)
1155 int irq = vms->irqmap[VIRT_MMIO] + i;
1156 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1158 sysbus_create_simple("virtio-mmio", base,
1159 qdev_get_gpio_in(vms->gic, irq));
1169 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1171 int irq = vms->irqmap[VIRT_MMIO] + i;
1172 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1175 qemu_fdt_add_subnode(ms->fdt, nodename);
1176 qemu_fdt_setprop_string(ms->fdt, nodename,
1178 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1180 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1183 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1200 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1202 qdev_prop_set_uint8(dev, "device-width", 2);
1203 qdev_prop_set_bit(dev, "big-endian", false);
1217 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1218 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1229 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1249 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1250 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1252 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1254 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1262 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1263 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1270 qemu_fdt_add_subnode(ms->fdt, nodename);
1271 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1272 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1275 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1283 qemu_fdt_add_subnode(ms->fdt, nodename);
1284 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1285 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1287 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1288 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1289 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1293 qemu_fdt_add_subnode(ms->fdt, nodename);
1294 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1295 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1297 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1310 /* Map legacy -drive if=pflash to machine properties */
1311 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1312 pflash_cfi01_legacy_drive(vms->flash[i],
1318 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1320 bios_name = MACHINE(vms)->firmware;
1328 "specified with -bios or with -drive if=pflash... "
1333 /* Fall back to -bios */
1340 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1355 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1356 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1361 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1363 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1364 qemu_fdt_add_subnode(ms->fdt, nodename);
1365 qemu_fdt_setprop_string(ms->fdt, nodename,
1366 "compatible", "qemu,fw-cfg-mmio");
1367 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1369 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1402 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1405 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1416 const char compat[] = "arm,smmu-v3";
1417 int irq = vms->irqmap[VIRT_SMMU];
1419 hwaddr base = vms->memmap[VIRT_SMMU].base;
1420 hwaddr size = vms->memmap[VIRT_SMMU].size;
1421 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1425 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1431 if (!vmc->no_nested_smmu) {
1434 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1440 qdev_get_gpio_in(vms->gic, irq + i));
1444 qemu_fdt_add_subnode(ms->fdt, node);
1445 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1446 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1448 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1454 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1457 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1459 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1461 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1467 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1468 uint16_t bdf = vms->virtio_iommu_bdf;
1472 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1474 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1476 qemu_fdt_add_subnode(ms->fdt, node);
1477 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1478 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1482 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1483 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1486 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1487 0x0, vms->iommu_phandle, 0x0, bdf,
1488 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1493 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1494 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1495 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1496 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1497 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1498 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1502 int irq = vms->irqmap[VIRT_PCIE];
1517 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1518 base_ecam = vms->memmap[ecam_id].base;
1519 size_ecam = vms->memmap[ecam_id].size;
1524 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1535 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1539 if (vms->highmem_mmio) {
1543 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1554 qdev_get_gpio_in(vms->gic, irq + i));
1559 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1560 vms->bus = pci->bus;
1561 if (vms->bus) {
1562 pci_init_nic_devices(pci->bus, mc->default_nic);
1565 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1566 qemu_fdt_add_subnode(ms->fdt, nodename);
1567 qemu_fdt_setprop_string(ms->fdt, nodename,
1568 "compatible", "pci-host-ecam-generic");
1569 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1570 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1571 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1572 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1573 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1574 nr_pcie_buses - 1);
1575 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1577 if (vms->msi_phandle) {
1578 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1579 0, vms->msi_phandle, 0, 0x10000);
1582 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1585 if (vms->highmem_mmio) {
1586 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1602 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1603 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1605 if (vms->iommu) {
1606 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1608 switch (vms->iommu) {
1610 create_smmu(vms, vms->bus);
1611 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1612 0x0, vms->iommu_phandle, 0x0, 0x10000);
1628 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1630 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1632 vms->platform_bus_dev = dev;
1636 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1637 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1641 vms->memmap[VIRT_PLATFORM_BUS].base,
1661 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1662 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1665 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1670 qemu_fdt_add_subnode(ms->fdt, nodename);
1671 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1672 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1673 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1674 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1677 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1690 *fdt_size = board->fdt_size;
1691 return ms->fdt;
1709 vmc->smbios_old_sys_ver ? "1.0" : mc->name);
1712 mem_array.address = vms->memmap[VIRT_MEM].base;
1713 mem_array.length = ms->ram_size;
1721 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1723 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1735 struct arm_boot_info *info = &vms->bootinfo;
1745 if (info->dtb_filename == NULL) {
1746 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1747 vms->memmap[VIRT_PLATFORM_BUS].base,
1748 vms->memmap[VIRT_PLATFORM_BUS].size,
1749 vms->irqmap[VIRT_PLATFORM_BUS]);
1751 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1755 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1766 if (!vmc->disallow_affinity_adjustment) {
1767 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1768 * GIC's target-list limitations. 32-bit KVM hosts currently
1772 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1775 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1788 &vms->highmem_redists,
1789 &vms->highmem_ecam,
1790 &vms->highmem_mmio,
1793 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1795 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1797 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1812 vms->memmap[i].base = region_base;
1813 vms->memmap[i].size = region_size;
1825 if (vms->highmem_compact && !*region_enabled) {
1831 vms->highest_gpa = base - 1;
1842 vms->memmap = extended_memmap;
1845 vms->memmap[i] = base_memmap[i];
1848 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1850 ms->ram_slots);
1858 if (!vms->highmem) {
1870 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1871 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1877 pa_bits, memtop - BIT_ULL(pa_bits));
1884 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1885 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1889 vms->highest_gpa = memtop - 1;
1907 error_report("gic-version=host requires KVM");
1911 /* For KVM, gic-version=host means gic-version=max */
1930 * the end-user requested more than 8 VCPUs we now default
1977 * finalize_gic_version - Determines the final gic_version
1978 * according to the gic-version property
1985 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
2006 accel_name = "KVM with kernel-irqchip=off";
2009 if (module_object_class_by_name("arm-gicv3")) {
2011 if (vms->virt) {
2025 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2035 int max_cpus = MACHINE(vms)->smp.max_cpus;
2036 bool aarch64, pmu, steal_time;
2039 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2042 "kvm-steal-time", NULL);
2045 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2046 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2069 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2077 + cpu->cpu_index
2082 if (aarch64 && vms->highmem) {
2083 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2108 bool aarch64 = true;
2109 bool has_ged = !vmc->no_ged;
2110 unsigned int smp_cpus = machine->smp.cpus;
2111 unsigned int max_cpus = machine->smp.max_cpus;
2113 possible_cpus = mc->possible_cpu_arch_ids(machine);
2120 if (!vms->memmap) {
2130 cpuobj = object_new(possible_cpus->cpus[0].type);
2145 if (vms->secure) {
2149 * containing the system memory at low priority; any secure-only
2153 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2155 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2171 if (vms->secure && firmware_loaded) {
2172 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2173 } else if (vms->virt) {
2174 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2176 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2184 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2188 if (vms->highmem_redists) {
2195 "supported by machine 'mach-virt' (%d)",
2197 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2198 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2204 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2205 error_report("mach-virt: %s does not support providing "
2211 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2212 error_report("mach-virt: %s does not support providing "
2218 if (vms->mte && hvf_enabled()) {
2219 error_report("mach-virt: %s does not support providing "
2227 assert(possible_cpus->len == max_cpus);
2228 for (n = 0; n < possible_cpus->len; n++) {
2236 cpuobj = object_new(possible_cpus->cpus[n].type);
2237 object_property_set_int(cpuobj, "mp-affinity",
2238 possible_cpus->cpus[n].arch_id, NULL);
2241 cs->cpu_index = n;
2243 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2246 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2248 if (!vms->secure) {
2252 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2256 if (vmc->kvm_no_adjvtime &&
2257 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2258 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2261 if (vmc->no_kvm_steal_time &&
2262 object_property_find(cpuobj, "kvm-steal-time")) {
2263 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2266 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2270 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2274 if (object_property_find(cpuobj, "reset-cbar")) {
2275 object_property_set_int(cpuobj, "reset-cbar",
2276 vms->memmap[VIRT_CPUPERIPHS].base,
2282 if (vms->secure) {
2283 object_property_set_link(cpuobj, "secure-memory",
2287 if (vms->mte) {
2295 if (!object_property_find(cpuobj, "tag-memory")) {
2303 "tag-memory", UINT64_MAX / 32);
2305 if (vms->secure) {
2308 "secure-tag-memory",
2311 /* As with ram, secure-tag takes precedence over tag. */
2313 0, tag_sysmem, -1);
2317 object_property_set_link(cpuobj, "tag-memory",
2319 if (vms->secure) {
2320 object_property_set_link(cpuobj, "secure-tag-memory",
2341 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2342 !vmc->no_ns_el2_virt_timer_irq;
2347 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2348 machine->ram);
2361 * if a backend is configured explicitly via '-serial <backend>'.
2371 * aliases node information and /chosen/stdout-path regardless of
2374 * For similar back-compatibility reasons, if UART1 is the secure UART
2378 if (!vms->secure) {
2382 vms->second_ns_uart_present = true;
2387 if (vms->secure) {
2391 if (vms->secure) {
2396 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2397 machine->ram_size, "mach-virt.tag");
2400 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2406 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2407 vms->acpi_dev = create_acpi_ged(vms);
2412 if (vms->secure && !vmc->no_secure_gpio) {
2417 vms->powerdown_notifier.notify = virt_powerdown_req;
2418 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2426 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2427 rom_set_fw(vms->fw_cfg);
2431 if (machine->nvdimms_state->is_enabled) {
2434 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2438 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2440 vms->fw_cfg, OBJECT(vms));
2443 vms->bootinfo.ram_size = machine->ram_size;
2444 vms->bootinfo.board_id = -1;
2445 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2446 vms->bootinfo.get_dtb = machvirt_dtb;
2447 vms->bootinfo.skip_dtb_autoload = true;
2448 vms->bootinfo.firmware_loaded = firmware_loaded;
2449 vms->bootinfo.psci_conduit = vms->psci_conduit;
2450 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2452 vms->machine_done.notify = virt_machine_done;
2453 qemu_add_machine_init_done_notifier(&vms->machine_done);
2460 return vms->secure;
2467 vms->secure = value;
2474 return vms->virt;
2481 vms->virt = value;
2488 return vms->highmem;
2495 vms->highmem = value;
2502 return vms->highmem_compact;
2509 vms->highmem_compact = value;
2516 return vms->highmem_redists;
2523 vms->highmem_redists = value;
2530 return vms->highmem_ecam;
2537 vms->highmem_ecam = value;
2544 return vms->highmem_mmio;
2551 vms->highmem_mmio = value;
2559 return vms->its;
2566 vms->its = value;
2573 return vms->dtb_randomness;
2580 vms->dtb_randomness = value;
2587 return g_strdup(vms->oem_id);
2597 "User specified oem-id value is bigger than 6 bytes in size");
2601 strncpy(vms->oem_id, value, 6);
2608 return g_strdup(vms->oem_table_id);
2619 "User specified oem-table-id value is bigger than 8 bytes in size");
2622 strncpy(vms->oem_table_id, value, 8);
2628 if (vms->acpi == ON_OFF_AUTO_OFF) {
2638 OnOffAuto acpi = vms->acpi;
2648 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2655 return vms->ras;
2662 vms->ras = value;
2669 return vms->mte;
2676 vms->mte = value;
2684 switch (vms->gic_version) {
2703 vms->gic_version = VIRT_GIC_VERSION_4;
2705 vms->gic_version = VIRT_GIC_VERSION_3;
2707 vms->gic_version = VIRT_GIC_VERSION_2;
2709 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2711 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2713 error_setg(errp, "Invalid gic-version value");
2722 switch (vms->iommu) {
2737 vms->iommu = VIRT_IOMMU_SMMUV3;
2739 vms->iommu = VIRT_IOMMU_NONE;
2750 return vms->default_bus_bypass_iommu;
2758 vms->default_bus_bypass_iommu = value;
2765 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2767 assert(cpu_index < possible_cpus->len);
2768 return possible_cpus->cpus[cpu_index].props;
2773 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2775 return socket_id % ms->numa_state->num_nodes;
2781 unsigned int max_cpus = ms->smp.max_cpus;
2785 if (ms->possible_cpus) {
2786 assert(ms->possible_cpus->len == max_cpus);
2787 return ms->possible_cpus;
2790 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2792 ms->possible_cpus->len = max_cpus;
2793 for (n = 0; n < ms->possible_cpus->len; n++) {
2794 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2795 ms->possible_cpus->cpus[n].arch_id =
2798 assert(!mc->smp_props.dies_supported);
2799 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2800 ms->possible_cpus->cpus[n].props.socket_id =
2801 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2802 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2803 ms->possible_cpus->cpus[n].props.cluster_id =
2804 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2805 ms->possible_cpus->cpus[n].props.has_core_id = true;
2806 ms->possible_cpus->cpus[n].props.core_id =
2807 (n / ms->smp.threads) % ms->smp.cores;
2808 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2809 ms->possible_cpus->cpus[n].props.thread_id =
2810 n % ms->smp.threads;
2812 return ms->possible_cpus;
2822 if (!vms->acpi_dev) {
2824 "memory hotplug is not enabled: missing acpi-ged device");
2828 if (vms->mte) {
2833 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2834 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2851 nvdimm_plug(ms->nvdimms_state);
2854 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2872 if (vms->iommu != VIRT_IOMMU_NONE) {
2877 switch (vms->msi_controller) {
2884 base_memmap[VIRT_GIC_ITS].size - 1;
2889 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2898 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2908 if (vms->platform_bus_dev) {
2912 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2926 vms->iommu = VIRT_IOMMU_VIRTIO;
2927 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2937 if (!vms->acpi_dev) {
2939 "memory hotplug is not enabled: missing acpi-ged device");
2948 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2958 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
3012 * for arm64 kvm_type [7-0] encodes the requested number of bits
3026 requested_pa_size = 64 - clz64(vms->highest_gpa);
3036 error_report("-m and ,maxmem option values "
3040 return -1;
3060 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3073 error_report("-m and ,maxmem option values "
3077 return -1;
3089 ARM_CPU_TYPE_NAME("cortex-a7"),
3090 ARM_CPU_TYPE_NAME("cortex-a15"),
3092 ARM_CPU_TYPE_NAME("cortex-a35"),
3093 ARM_CPU_TYPE_NAME("cortex-a55"),
3094 ARM_CPU_TYPE_NAME("cortex-a72"),
3095 ARM_CPU_TYPE_NAME("cortex-a76"),
3096 ARM_CPU_TYPE_NAME("cortex-a710"),
3098 ARM_CPU_TYPE_NAME("neoverse-n1"),
3099 ARM_CPU_TYPE_NAME("neoverse-v1"),
3100 ARM_CPU_TYPE_NAME("neoverse-n2"),
3104 ARM_CPU_TYPE_NAME("cortex-a53"),
3105 ARM_CPU_TYPE_NAME("cortex-a57"),
3114 mc->init = machvirt_init;
3119 mc->max_cpus = 512;
3127 mc->block_default_type = IF_VIRTIO;
3128 mc->no_cdrom = 1;
3129 mc->pci_allow_0_address = true;
3130 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3131 mc->minimum_page_bits = 12;
3132 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3133 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3135 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3137 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3139 mc->valid_cpu_types = valid_cpu_types;
3140 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3141 mc->kvm_type = virt_kvm_type;
3142 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3143 assert(!mc->get_hotplug_handler);
3144 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3145 hc->pre_plug = virt_machine_device_pre_plug_cb;
3146 hc->plug = virt_machine_device_plug_cb;
3147 hc->unplug_request = virt_machine_device_unplug_request_cb;
3148 hc->unplug = virt_machine_device_unplug_cb;
3149 mc->nvdimm_supported = true;
3150 mc->smp_props.clusters_supported = true;
3151 mc->auto_enable_numa_with_memhp = true;
3152 mc->auto_enable_numa_with_memdev = true;
3154 mc->cpu_cluster_has_numa_boundary = true;
3155 mc->default_ram_id = "mach-virt.ram";
3156 mc->default_nic = "virtio-net-pci";
3182 object_class_property_add_bool(oc, "compact-highmem",
3185 object_class_property_set_description(oc, "compact-highmem",
3189 object_class_property_add_bool(oc, "highmem-redists",
3192 object_class_property_set_description(oc, "highmem-redists",
3197 object_class_property_add_bool(oc, "highmem-ecam",
3200 object_class_property_set_description(oc, "highmem-ecam",
3204 object_class_property_add_bool(oc, "highmem-mmio",
3207 object_class_property_set_description(oc, "highmem-mmio",
3211 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3213 object_class_property_set_description(oc, "gic-version",
3222 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3225 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3247 object_class_property_add_bool(oc, "dtb-randomness",
3250 object_class_property_set_description(oc, "dtb-randomness",
3252 "non-deterministic dtb nodes to guest");
3254 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3257 object_class_property_set_description(oc, "dtb-kaslr-seed",
3258 "Deprecated synonym of dtb-randomness");
3260 object_class_property_add_str(oc, "x-oem-id",
3263 object_class_property_set_description(oc, "x-oem-id",
3269 object_class_property_add_str(oc, "x-oem-table-id",
3272 object_class_property_set_description(oc, "x-oem-table-id",
3288 vms->secure = false;
3291 vms->virt = false;
3294 vms->highmem = true;
3295 vms->highmem_compact = !vmc->no_highmem_compact;
3296 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3298 vms->highmem_ecam = !vmc->no_highmem_ecam;
3299 vms->highmem_mmio = true;
3300 vms->highmem_redists = true;
3302 if (vmc->no_its) {
3303 vms->its = false;
3306 vms->its = true;
3308 if (vmc->no_tcg_its) {
3309 vms->tcg_its = false;
3311 vms->tcg_its = true;
3316 vms->iommu = VIRT_IOMMU_NONE;
3319 vms->default_bus_bypass_iommu = false;
3322 vms->ras = false;
3325 vms->mte = false;
3327 /* Supply kaslr-seed and rng-seed by default */
3328 vms->dtb_randomness = true;
3330 vms->irqmap = a15irqmap;
3334 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3335 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3368 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3369 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3370 vmc->no_nested_smmu = true;
3377 mc->smbios_memory_device_size = 16 * GiB;
3378 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3387 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3393 vmc->no_ns_el2_virt_timer_irq = true;
3400 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3407 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3414 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3423 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3425 vmc->no_highmem_compact = true;
3432 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3441 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3442 vmc->no_tcg_lpa2 = true;
3451 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3452 mc->smp_props.prefer_sockets = true;
3453 vmc->no_cpu_topology = true;
3456 vmc->no_tcg_its = true;
3463 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3472 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3473 vmc->no_secure_gpio = true;
3482 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3483 vmc->no_kvm_steal_time = true;
3492 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3493 mc->numa_mem_supported = true;
3494 vmc->acpi_expose_flash = true;
3495 mc->auto_enable_numa_with_memdev = false;
3504 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3505 vmc->kvm_no_adjvtime = true;
3514 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3515 vmc->no_ged = true;
3516 mc->auto_enable_numa_with_memhp = false;
3523 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3530 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3537 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3546 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3547 vmc->no_highmem_ecam = true;
3548 mc->max_cpus = 255;
3557 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3558 vmc->smbios_old_sys_ver = true;
3565 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3567 mc->ignore_memory_transaction_failures = true;
3574 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3583 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3585 * our timers were edge-triggered, not level-triggered.
3587 vmc->claim_edge_triggered_timers = true;
3596 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3598 vmc->no_its = true;
3599 /* Stick with 1K pages for migration compatibility */
3600 mc->minimum_page_bits = 0;
3609 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3610 vmc->disallow_affinity_adjustment = true;
3612 vmc->no_pmu = true;