Lines Matching +full:0 +full:x09010000
148 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
156 * Note that devices should generally be placed at multiples of 0x10000,
160 /* Space up to 0x8000000 is reserved for a boot ROM */
161 [VIRT_FLASH] = { 0, 0x08000000 },
162 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
164 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
165 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
166 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
167 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
168 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
170 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
172 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
173 [VIRT_UART0] = { 0x09000000, 0x00001000 },
174 [VIRT_RTC] = { 0x09010000, 0x00001000 },
175 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
176 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
177 [VIRT_UART1] = { 0x09040000, 0x00001000 },
178 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
179 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
180 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
181 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
182 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
183 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
184 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
186 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
187 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
188 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
189 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
190 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
213 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
214 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
216 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
253 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); in ns_el2_virt_timer_present()
275 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
276 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
288 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0); in create_fdt()
313 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); in create_fdt()
319 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { in create_fdt()
324 for (i = 0; i < nb_numa_nodes; i++) { in create_fdt()
325 for (j = 0; j < nb_numa_nodes; j++) { in create_fdt()
327 matrix[idx + 0] = cpu_to_be32(i); in create_fdt()
380 armcpu = ARM_CPU(qemu_get_cpu(0)); in fdt_add_timer_nodes()
382 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; in fdt_add_timer_nodes()
389 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); in fdt_add_timer_nodes()
427 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs in fdt_add_cpu_nodes()
436 for (cpu = 0; cpu < smp_cpus; cpu++) { in fdt_add_cpu_nodes()
447 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
449 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { in fdt_add_cpu_nodes()
504 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { in fdt_add_cpu_nodes()
542 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); in fdt_add_its_gic_node()
562 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); in fdt_add_v2m_gic_node()
582 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_gic_node()
583 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); in fdt_add_gic_node()
584 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); in fdt_add_gic_node()
585 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); in fdt_add_gic_node()
695 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); in create_acpi_ged()
697 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); in create_acpi_ged()
723 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); in create_its()
739 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); in create_v2m()
741 for (i = 0; i < NUM_GICV2M_SPIS; i++) { in create_v2m()
758 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); in gicv3_nmi_present()
772 uint32_t nb_redist_regions = 0; in create_gic()
844 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); in create_gic()
864 for (i = 0; i < smp_cpus; i++) { in create_gic()
878 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { in create_gic()
888 0, irq); in create_gic()
895 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, in create_gic()
931 const char compat[] = "arm,pl011\0arm,primecell"; in create_uart()
932 const char clocknames[] = "uartclk\0apb_pclk"; in create_uart()
940 sysbus_mmio_get_region(s, 0)); in create_uart()
941 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); in create_uart()
982 const char compat[] = "arm,pl031\0arm,primecell"; in create_rtc()
1009 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); in virt_powerdown_req()
1029 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0); in create_gpio_keys()
1032 #define SECURE_GPIO_POWEROFF 0
1045 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); in create_secure_gpio_pwr()
1047 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); in create_secure_gpio_pwr()
1053 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); in create_secure_gpio_pwr()
1062 "gpios", phandle, SECURE_GPIO_RESET, 0); in create_secure_gpio_pwr()
1076 const char compat[] = "arm,pl061\0arm,primecell"; in create_gpio_devices()
1081 /* Pull lines down to 0 if not driven by the PL061 */ in create_gpio_devices()
1082 qdev_prop_set_uint32(pl061_dev, "pullups", 0); in create_gpio_devices()
1083 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); in create_gpio_devices()
1086 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); in create_gpio_devices()
1087 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); in create_gpio_devices()
1096 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); in create_gpio_devices()
1152 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { in create_virtio_devices()
1167 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { in create_virtio_devices()
1181 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_virtio_devices()
1202 qdev_prop_set_uint16(dev, "id0", 0x89); in virt_flash_create1()
1203 qdev_prop_set_uint16(dev, "id1", 0x18); in virt_flash_create1()
1204 qdev_prop_set_uint16(dev, "id2", 0x00); in virt_flash_create1()
1205 qdev_prop_set_uint16(dev, "id3", 0x00); in virt_flash_create1()
1215 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); in virt_flash_create()
1232 0)); in virt_flash_map1()
1250 virt_flash_map1(vms->flash[0], flashbase, flashsize, in virt_flash_map()
1309 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { in virt_firmware_init()
1311 drive_get(IF_PFLASH, 0, i)); in virt_firmware_init()
1316 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); in virt_firmware_init()
1338 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); in virt_firmware_init()
1341 if (image_size < 0) { in virt_firmware_init()
1367 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_fw_cfg()
1377 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; in create_pcie_irq_map()
1380 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { in create_pcie_irq_map()
1381 for (pin = 0; pin < 4; pin++) { in create_pcie_irq_map()
1388 devfn << 8, 0, 0, /* devfn */ in create_pcie_irq_map()
1390 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ in create_pcie_irq_map()
1393 for (i = 0; i < 10; i++) { in create_pcie_irq_map()
1404 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ in create_pcie_irq_map()
1405 0, 0, in create_pcie_irq_map()
1406 0x7 /* PCI irq */); in create_pcie_irq_map()
1419 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; in create_smmu()
1435 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); in create_smmu()
1436 for (i = 0; i < NUM_SMMU_IRQS; i++) { in create_smmu()
1455 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); in create_smmu()
1465 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; in create_virtio_iommu_dt_bindings()
1477 1, bdf << 8, 1, 0, 1, 0, in create_virtio_iommu_dt_bindings()
1478 1, 0, 1, 0); in create_virtio_iommu_dt_bindings()
1485 0x0, vms->iommu_phandle, 0x0, bdf, in create_virtio_iommu_dt_bindings()
1486 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); in create_virtio_iommu_dt_bindings()
1521 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); in create_pcie()
1523 ecam_reg, 0, size_ecam); in create_pcie()
1550 for (i = 0; i < GPEX_NUM_IRQS; i++) { in create_pcie()
1570 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); in create_pcie()
1571 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, in create_pcie()
1573 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_pcie()
1577 0, vms->msi_phandle, 0, 0x10000); in create_pcie()
1585 1, FDT_PCI_RANGE_IOPORT, 2, 0, in create_pcie()
1594 1, FDT_PCI_RANGE_IOPORT, 2, 0, in create_pcie()
1610 0x0, vms->iommu_phandle, 0x0, 0x10000); in create_pcie()
1633 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { in create_platform_bus()
1640 sysbus_mmio_get_region(s, 0)); in create_platform_bus()
1749 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { in virt_machine_done()
1842 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { in virt_set_memmap()
1891 if (device_memory_size > 0) { in virt_set_memmap()
1984 int gics_supported = 0; in finalize_gic_version()
2128 cpuobj = object_new(possible_cpus->cpus[0].type); in machvirt_init()
2153 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); in machvirt_init()
2226 for (n = 0; n < possible_cpus->len; n++) { in machvirt_init()
2311 0, tag_sysmem, -1); in machvirt_init()
2384 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); in machvirt_init()
2791 for (n = 0; n < ms->possible_cpus->len; n++) { in virt_possible_cpu_arch_ids()
2866 hwaddr db_start = 0, db_end = 0; in virt_machine_device_pre_plug_cb()
2880 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; in virt_machine_device_pre_plug_cb()
2890 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", in virt_machine_device_pre_plug_cb()
3010 * for arm64 kvm_type [7-0] encodes the requested number of bits
3043 * must be 0. in virt_kvm_type()
3045 return fixed_ipa ? 0 : requested_pa_size; in virt_kvm_type()
3378 DEFINE_VIRT_MACHINE(9, 0)
3407 DEFINE_VIRT_MACHINE(8, 0)
3432 DEFINE_VIRT_MACHINE(7, 0)
3463 DEFINE_VIRT_MACHINE(6, 0)
3495 DEFINE_VIRT_MACHINE(5, 0)
3523 DEFINE_VIRT_MACHINE(4, 0)
3537 DEFINE_VIRT_MACHINE(3, 0)
3598 mc->minimum_page_bits = 0; in virt_machine_2_7_options()