Lines Matching +full:level +full:- +full:detect
2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
11 * Copyright (c) 2003-2004 Fabrice Bellard
26 * Contributions after 2012-01-13 are licensed under the terms of the
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
37 #include "qemu/error-report.h"
39 #include "chardev/char-fe.h"
40 #include "chardev/char-serial.h"
48 #include "target/arm/cpu-qom.h"
53 - Implement cp15, c14 ?
54 - Implement cp15, c15 !!! (idle used in L)
55 - Implement idle mode handling/DIM
56 - Implement sleep mode/Wake sources
57 - Implement reset control
58 - Implement memory control regs
59 - PCMCIA handling
60 - Maybe support MBGNT/MBREQ
61 - DMA channels
62 - GPCLK
63 - IrDA
64 - MCP
65 - Enhance UART with modem signals
111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update()
112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update()
115 static void strongarm_pic_set_irq(void *opaque, int irq, int level) in strongarm_pic_set_irq() argument
119 if (level) { in strongarm_pic_set_irq()
120 s->pending |= 1 << irq; in strongarm_pic_set_irq()
122 s->pending &= ~(1 << irq); in strongarm_pic_set_irq()
135 return s->pending & ~s->is_fiq & s->enabled; in strongarm_pic_mem_read()
137 return s->enabled; in strongarm_pic_mem_read()
139 return s->is_fiq; in strongarm_pic_mem_read()
141 return s->int_idle == 0; in strongarm_pic_mem_read()
143 return s->pending & s->is_fiq & s->enabled; in strongarm_pic_mem_read()
145 return s->pending; in strongarm_pic_mem_read()
161 s->enabled = value; in strongarm_pic_mem_write()
164 s->is_fiq = value; in strongarm_pic_mem_write()
167 s->int_idle = (value & 1) ? 0 : ~0; in strongarm_pic_mem_write()
191 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, in strongarm_pic_initfn()
193 sysbus_init_mmio(sbd, &s->iomem); in strongarm_pic_initfn()
194 sysbus_init_irq(sbd, &s->irq); in strongarm_pic_initfn()
195 sysbus_init_irq(sbd, &s->fiq); in strongarm_pic_initfn()
222 dc->desc = "StrongARM PIC"; in strongarm_pic_class_init()
223 dc->vmsd = &vmstate_strongarm_pic_regs; in strongarm_pic_class_init()
234 /* Real-Time Clock */
249 #define TYPE_STRONGARM_RTC "strongarm-rtc"
269 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); in strongarm_rtc_int_update()
270 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); in strongarm_rtc_int_update()
276 s->last_rcnr += ((rt - s->last_hz) << 15) / in strongarm_rtc_hzupdate()
277 (1000 * ((s->rttr & 0xffff) + 1)); in strongarm_rtc_hzupdate()
278 s->last_hz = rt; in strongarm_rtc_hzupdate()
283 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { in strongarm_rtc_timer_update()
284 timer_mod(s->rtc_hz, s->last_hz + 1000); in strongarm_rtc_timer_update()
286 timer_del(s->rtc_hz); in strongarm_rtc_timer_update()
289 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { in strongarm_rtc_timer_update()
290 timer_mod(s->rtc_alarm, s->last_hz + in strongarm_rtc_timer_update()
291 (((s->rtar - s->last_rcnr) * 1000 * in strongarm_rtc_timer_update()
292 ((s->rttr & 0xffff) + 1)) >> 15)); in strongarm_rtc_timer_update()
294 timer_del(s->rtc_alarm); in strongarm_rtc_timer_update()
301 s->rtsr |= RTSR_AL; in strongarm_rtc_alarm_tick()
309 s->rtsr |= RTSR_HZ; in strongarm_rtc_hz_tick()
321 return s->rttr; in strongarm_rtc_read()
323 return s->rtsr; in strongarm_rtc_read()
325 return s->rtar; in strongarm_rtc_read()
327 return s->last_rcnr + in strongarm_rtc_read()
328 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / in strongarm_rtc_read()
329 (1000 * ((s->rttr & 0xffff) + 1)); in strongarm_rtc_read()
347 s->rttr = value; in strongarm_rtc_write()
352 old_rtsr = s->rtsr; in strongarm_rtc_write()
353 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | in strongarm_rtc_write()
354 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); in strongarm_rtc_write()
356 if (s->rtsr != old_rtsr) { in strongarm_rtc_write()
364 s->rtar = value; in strongarm_rtc_write()
370 s->last_rcnr = value; in strongarm_rtc_write()
393 s->rttr = 0x0; in strongarm_rtc_init()
394 s->rtsr = 0; in strongarm_rtc_init()
398 s->last_rcnr = (uint32_t) mktimegm(&tm); in strongarm_rtc_init()
399 s->last_hz = qemu_clock_get_ms(rtc_clock); in strongarm_rtc_init()
401 sysbus_init_irq(dev, &s->rtc_irq); in strongarm_rtc_init()
402 sysbus_init_irq(dev, &s->rtc_hz_irq); in strongarm_rtc_init()
404 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, in strongarm_rtc_init()
406 sysbus_init_mmio(dev, &s->iomem); in strongarm_rtc_init()
412 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); in strongarm_rtc_realize()
413 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); in strongarm_rtc_realize()
436 .name = "strongarm-rtc",
456 dc->desc = "StrongARM RTC Controller"; in strongarm_rtc_sysbus_class_init()
457 dc->vmsd = &vmstate_strongarm_rtc_regs; in strongarm_rtc_sysbus_class_init()
458 dc->realize = strongarm_rtc_realize; in strongarm_rtc_sysbus_class_init()
479 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
505 qemu_set_irq(s->irqs[i], s->status & (1 << i)); in strongarm_gpio_irq_update()
508 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); in strongarm_gpio_irq_update()
511 static void strongarm_gpio_set(void *opaque, int line, int level) in strongarm_gpio_set() argument
518 if (level) { in strongarm_gpio_set()
519 s->status |= s->rising & mask & in strongarm_gpio_set()
520 ~s->ilevel & ~s->dir; in strongarm_gpio_set()
521 s->ilevel |= mask; in strongarm_gpio_set()
523 s->status |= s->falling & mask & in strongarm_gpio_set()
524 s->ilevel & ~s->dir; in strongarm_gpio_set()
525 s->ilevel &= ~mask; in strongarm_gpio_set()
528 if (s->status & mask) { in strongarm_gpio_set()
535 uint32_t level, diff; in strongarm_gpio_handler_update() local
538 level = s->olevel & s->dir; in strongarm_gpio_handler_update()
540 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { in strongarm_gpio_handler_update()
542 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_gpio_handler_update()
545 s->prev_level = level; in strongarm_gpio_handler_update()
554 case GPDR: /* GPIO Pin-Direction registers */ in strongarm_gpio_read()
555 return s->dir; in strongarm_gpio_read()
557 case GPSR: /* GPIO Pin-Output Set registers */ in strongarm_gpio_read()
562 case GPCR: /* GPIO Pin-Output Clear registers */ in strongarm_gpio_read()
567 case GRER: /* GPIO Rising-Edge Detect Enable registers */ in strongarm_gpio_read()
568 return s->rising; in strongarm_gpio_read()
570 case GFER: /* GPIO Falling-Edge Detect Enable registers */ in strongarm_gpio_read()
571 return s->falling; in strongarm_gpio_read()
574 return s->gafr; in strongarm_gpio_read()
576 case GPLR: /* GPIO Pin-Level registers */ in strongarm_gpio_read()
577 return (s->olevel & s->dir) | in strongarm_gpio_read()
578 (s->ilevel & ~s->dir); in strongarm_gpio_read()
580 case GEDR: /* GPIO Edge Detect Status registers */ in strongarm_gpio_read()
581 return s->status; in strongarm_gpio_read()
598 case GPDR: /* GPIO Pin-Direction registers */ in strongarm_gpio_write()
599 s->dir = value & 0x0fffffff; in strongarm_gpio_write()
603 case GPSR: /* GPIO Pin-Output Set registers */ in strongarm_gpio_write()
604 s->olevel |= value & 0x0fffffff; in strongarm_gpio_write()
608 case GPCR: /* GPIO Pin-Output Clear registers */ in strongarm_gpio_write()
609 s->olevel &= ~value; in strongarm_gpio_write()
613 case GRER: /* GPIO Rising-Edge Detect Enable registers */ in strongarm_gpio_write()
614 s->rising = value; in strongarm_gpio_write()
617 case GFER: /* GPIO Falling-Edge Detect Enable registers */ in strongarm_gpio_write()
618 s->falling = value; in strongarm_gpio_write()
622 s->gafr = value; in strongarm_gpio_write()
625 case GEDR: /* GPIO Edge Detect Status registers */ in strongarm_gpio_write()
626 s->status &= ~value; in strongarm_gpio_write()
668 qdev_init_gpio_out(dev, s->handler, 28); in strongarm_gpio_initfn()
670 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, in strongarm_gpio_initfn()
673 sysbus_init_mmio(sbd, &s->iomem); in strongarm_gpio_initfn()
675 sysbus_init_irq(sbd, &s->irqs[i]); in strongarm_gpio_initfn()
677 sysbus_init_irq(sbd, &s->irqX); in strongarm_gpio_initfn()
681 .name = "strongarm-gpio",
701 dc->desc = "StrongARM GPIO controller"; in strongarm_gpio_class_init()
702 dc->vmsd = &vmstate_strongarm_gpio_regs; in strongarm_gpio_class_init()
720 #define TYPE_STRONGARM_PPC "strongarm-ppc"
739 static void strongarm_ppc_set(void *opaque, int line, int level) in strongarm_ppc_set() argument
743 if (level) { in strongarm_ppc_set()
744 s->ilevel |= 1 << line; in strongarm_ppc_set()
746 s->ilevel &= ~(1 << line); in strongarm_ppc_set()
752 uint32_t level, diff; in strongarm_ppc_handler_update() local
755 level = s->olevel & s->dir; in strongarm_ppc_handler_update()
757 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { in strongarm_ppc_handler_update()
759 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_ppc_handler_update()
762 s->prev_level = level; in strongarm_ppc_handler_update()
772 return s->dir | ~0x3fffff; in strongarm_ppc_read()
775 return (s->olevel & s->dir) | in strongarm_ppc_read()
776 (s->ilevel & ~s->dir) | in strongarm_ppc_read()
780 return s->ppar | ~0x41000; in strongarm_ppc_read()
783 return s->psdr; in strongarm_ppc_read()
786 return s->ppfr | ~0x7f001; in strongarm_ppc_read()
804 s->dir = value & 0x3fffff; in strongarm_ppc_write()
809 s->olevel = value & s->dir & 0x3fffff; in strongarm_ppc_write()
814 s->ppar = value & 0x41000; in strongarm_ppc_write()
818 s->psdr = value & 0x3fffff; in strongarm_ppc_write()
822 s->ppfr = value & 0x7f001; in strongarm_ppc_write()
845 qdev_init_gpio_out(dev, s->handler, 22); in strongarm_ppc_init()
847 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, in strongarm_ppc_init()
850 sysbus_init_mmio(sbd, &s->iomem); in strongarm_ppc_init()
854 .name = "strongarm-ppc",
873 dc->desc = "StrongARM PPC controller"; in strongarm_ppc_class_init()
874 dc->vmsd = &vmstate_strongarm_ppc_regs; in strongarm_ppc_class_init()
897 #define UTCR0_DSS (1 << 3) /* 8-bit data */
923 #define TYPE_STRONGARM_UART "strongarm-uart"
956 if (s->tx_len != 8) { in strongarm_uart_update_status()
960 if (s->rx_len != 0) { in strongarm_uart_update_status()
961 uint16_t ent = s->rx_fifo[s->rx_start]; in strongarm_uart_update_status()
965 s->utsr1 |= UTSR1_PRE; in strongarm_uart_update_status()
968 s->utsr1 |= UTSR1_FRE; in strongarm_uart_update_status()
971 s->utsr1 |= UTSR1_ROR; in strongarm_uart_update_status()
975 s->utsr1 = utsr1; in strongarm_uart_update_status()
980 uint16_t utsr0 = s->utsr0 & in strongarm_uart_update_int_status()
984 if ((s->utcr3 & UTCR3_TXE) && in strongarm_uart_update_int_status()
985 (s->utcr3 & UTCR3_TIE) && in strongarm_uart_update_int_status()
986 s->tx_len <= 4) { in strongarm_uart_update_int_status()
990 if ((s->utcr3 & UTCR3_RXE) && in strongarm_uart_update_int_status()
991 (s->utcr3 & UTCR3_RIE) && in strongarm_uart_update_int_status()
992 s->rx_len > 4) { in strongarm_uart_update_int_status()
996 for (i = 0; i < s->rx_len && i < 4; i++) in strongarm_uart_update_int_status()
997 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { in strongarm_uart_update_int_status()
1002 s->utsr0 = utsr0; in strongarm_uart_update_int_status()
1003 qemu_set_irq(s->irq, utsr0); in strongarm_uart_update_int_status()
1013 if (s->utcr0 & UTCR0_PE) { in strongarm_uart_update_parameters()
1016 if (s->utcr0 & UTCR0_OES) { in strongarm_uart_update_parameters()
1024 if (s->utcr0 & UTCR0_SBS) { in strongarm_uart_update_parameters()
1030 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; in strongarm_uart_update_parameters()
1032 speed = 3686400 / 16 / (s->brd + 1); in strongarm_uart_update_parameters()
1037 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; in strongarm_uart_update_parameters()
1038 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in strongarm_uart_update_parameters()
1040 trace_strongarm_uart_update_parameters((s->chr.chr ? in strongarm_uart_update_parameters()
1041 s->chr.chr->label : "NULL") ?: in strongarm_uart_update_parameters()
1053 if (s->rx_len) { in strongarm_uart_rx_to()
1054 s->utsr0 |= UTSR0_RID; in strongarm_uart_rx_to()
1061 if ((s->utcr3 & UTCR3_RXE) == 0) { in strongarm_uart_rx_push()
1066 if (s->wait_break_end) { in strongarm_uart_rx_push()
1067 s->utsr0 |= UTSR0_REB; in strongarm_uart_rx_push()
1068 s->wait_break_end = false; in strongarm_uart_rx_push()
1071 if (s->rx_len < 12) { in strongarm_uart_rx_push()
1072 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; in strongarm_uart_rx_push()
1073 s->rx_len++; in strongarm_uart_rx_push()
1075 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; in strongarm_uart_rx_push()
1082 if (s->rx_len == 12) { in strongarm_uart_can_receive()
1086 if (s->rx_len < 8) { in strongarm_uart_can_receive()
1087 return 8 - s->rx_len; in strongarm_uart_can_receive()
1102 timer_mod(s->rx_timeout_timer, in strongarm_uart_receive()
1103 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); in strongarm_uart_receive()
1113 s->utsr0 |= UTSR0_RBB; in strongarm_uart_event()
1115 s->wait_break_end = true; in strongarm_uart_event()
1126 if (s->utcr3 & UTCR3_LBM) /* loopback */ { in strongarm_uart_tx()
1127 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); in strongarm_uart_tx()
1128 } else if (qemu_chr_fe_backend_connected(&s->chr)) { in strongarm_uart_tx()
1131 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); in strongarm_uart_tx()
1134 s->tx_start = (s->tx_start + 1) % 8; in strongarm_uart_tx()
1135 s->tx_len--; in strongarm_uart_tx()
1136 if (s->tx_len) { in strongarm_uart_tx()
1137 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); in strongarm_uart_tx()
1151 return s->utcr0; in strongarm_uart_read()
1154 return s->brd >> 8; in strongarm_uart_read()
1157 return s->brd & 0xff; in strongarm_uart_read()
1160 return s->utcr3; in strongarm_uart_read()
1163 if (s->rx_len != 0) { in strongarm_uart_read()
1164 ret = s->rx_fifo[s->rx_start]; in strongarm_uart_read()
1165 s->rx_start = (s->rx_start + 1) % 12; in strongarm_uart_read()
1166 s->rx_len--; in strongarm_uart_read()
1174 return s->utsr0; in strongarm_uart_read()
1177 return s->utsr1; in strongarm_uart_read()
1194 s->utcr0 = value & 0x7f; in strongarm_uart_write()
1199 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); in strongarm_uart_write()
1204 s->brd = (s->brd & 0xf00) | (value & 0xff); in strongarm_uart_write()
1209 s->utcr3 = value & 0x3f; in strongarm_uart_write()
1210 if ((s->utcr3 & UTCR3_RXE) == 0) { in strongarm_uart_write()
1211 s->rx_len = 0; in strongarm_uart_write()
1213 if ((s->utcr3 & UTCR3_TXE) == 0) { in strongarm_uart_write()
1214 s->tx_len = 0; in strongarm_uart_write()
1221 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { in strongarm_uart_write()
1222 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; in strongarm_uart_write()
1223 s->tx_len++; in strongarm_uart_write()
1226 if (s->tx_len == 1) { in strongarm_uart_write()
1233 s->utsr0 = s->utsr0 & ~(value & in strongarm_uart_write()
1256 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, in strongarm_uart_init()
1258 sysbus_init_mmio(dev, &s->iomem); in strongarm_uart_init()
1259 sysbus_init_irq(dev, &s->irq); in strongarm_uart_init()
1266 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in strongarm_uart_realize()
1269 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); in strongarm_uart_realize()
1270 qemu_chr_fe_set_handlers(&s->chr, in strongarm_uart_realize()
1281 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ in strongarm_uart_reset()
1282 s->brd = 23; /* 9600 */ in strongarm_uart_reset()
1283 /* enable send & recv - this actually violates spec */ in strongarm_uart_reset()
1284 s->utcr3 = UTCR3_TXE | UTCR3_RXE; in strongarm_uart_reset()
1286 s->rx_len = s->tx_len = 0; in strongarm_uart_reset()
1302 if (s->tx_len) { in strongarm_uart_post_load()
1307 if (s->rx_len) { in strongarm_uart_post_load()
1308 timer_mod(s->rx_timeout_timer, in strongarm_uart_post_load()
1309 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); in strongarm_uart_post_load()
1316 .name = "strongarm-uart",
1344 dc->desc = "StrongARM UART controller"; in strongarm_uart_class_init()
1346 dc->vmsd = &vmstate_strongarm_uart_regs; in strongarm_uart_class_init()
1348 dc->realize = strongarm_uart_realize; in strongarm_uart_class_init()
1361 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1403 int level = 0; in strongarm_ssp_int_update() local
1405 level |= (s->sssr & SSSR_ROR); in strongarm_ssp_int_update()
1406 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); in strongarm_ssp_int_update()
1407 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); in strongarm_ssp_int_update()
1408 qemu_set_irq(s->irq, level); in strongarm_ssp_int_update()
1413 s->sssr &= ~SSSR_TFS; in strongarm_ssp_fifo_update()
1414 s->sssr &= ~SSSR_TNF; in strongarm_ssp_fifo_update()
1415 if (s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_fifo_update()
1416 if (s->rx_level >= 4) { in strongarm_ssp_fifo_update()
1417 s->sssr |= SSSR_RFS; in strongarm_ssp_fifo_update()
1419 s->sssr &= ~SSSR_RFS; in strongarm_ssp_fifo_update()
1421 if (s->rx_level) { in strongarm_ssp_fifo_update()
1422 s->sssr |= SSSR_RNE; in strongarm_ssp_fifo_update()
1424 s->sssr &= ~SSSR_RNE; in strongarm_ssp_fifo_update()
1428 s->sssr |= SSSR_TFS; in strongarm_ssp_fifo_update()
1429 s->sssr |= SSSR_TNF; in strongarm_ssp_fifo_update()
1443 return s->sscr[0]; in strongarm_ssp_read()
1445 return s->sscr[1]; in strongarm_ssp_read()
1447 return s->sssr; in strongarm_ssp_read()
1449 if (~s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_read()
1452 if (s->rx_level < 1) { in strongarm_ssp_read()
1456 s->rx_level--; in strongarm_ssp_read()
1457 retval = s->rx_fifo[s->rx_start++]; in strongarm_ssp_read()
1458 s->rx_start &= 0x7; in strongarm_ssp_read()
1477 s->sscr[0] = value & 0xffbf; in strongarm_ssp_write()
1478 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { in strongarm_ssp_write()
1483 s->sssr = 0; in strongarm_ssp_write()
1484 s->rx_level = 0; in strongarm_ssp_write()
1490 s->sscr[1] = value & 0x2f; in strongarm_ssp_write()
1500 s->sssr &= ~(value & SSSR_RW); in strongarm_ssp_write()
1505 if (SSCR0_UWIRE(s->sscr[0])) { in strongarm_ssp_write()
1509 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; in strongarm_ssp_write()
1514 if (s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_write()
1516 if (s->sscr[1] & SSCR1_LBM) { in strongarm_ssp_write()
1519 readval = ssi_transfer(s->bus, value); in strongarm_ssp_write()
1522 if (s->rx_level < 0x08) { in strongarm_ssp_write()
1523 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; in strongarm_ssp_write()
1525 s->sssr |= SSSR_ROR; in strongarm_ssp_write()
1560 sysbus_init_irq(sbd, &s->irq); in strongarm_ssp_init()
1562 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, in strongarm_ssp_init()
1564 sysbus_init_mmio(sbd, &s->iomem); in strongarm_ssp_init()
1566 s->bus = ssi_create_bus(dev, "ssi"); in strongarm_ssp_init()
1573 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ in strongarm_ssp_reset()
1574 s->rx_start = 0; in strongarm_ssp_reset()
1575 s->rx_level = 0; in strongarm_ssp_reset()
1579 .name = "strongarm-ssp",
1597 dc->desc = "StrongARM SSP controller"; in strongarm_ssp_class_init()
1599 dc->vmsd = &vmstate_strongarm_ssp_regs; in strongarm_ssp_class_init()
1623 s->cpu = ARM_CPU(cpu_create(cpu_type)); in sa1110_init()
1625 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, in sa1110_init()
1626 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), in sa1110_init()
1627 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), in sa1110_init()
1630 sysbus_create_varargs("pxa25x-timer", 0x90000000, in sa1110_init()
1631 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), in sa1110_init()
1632 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), in sa1110_init()
1633 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), in sa1110_init()
1634 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), in sa1110_init()
1638 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); in sa1110_init()
1640 s->gpio = strongarm_gpio_init(0x90040000, s->pic); in sa1110_init()
1642 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); in sa1110_init()
1651 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); in sa1110_init()
1654 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, in sa1110_init()
1655 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); in sa1110_init()
1656 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); in sa1110_init()