Lines Matching +full:0 +full:x40024000
37 #define GPIO_A 0
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
105 0x31c0, /* 1 Mhz */
106 0x1ae0, /* 1.8432 Mhz */
107 0x18c0, /* 2 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
110 0x1ae2, /* 3.6864 Mhz */
111 0x0c40, /* 4 Mhz */
112 0x98bc, /* 4.906 Mhz */
113 0x935b, /* 4.9152 Mhz */
114 0x09c0, /* 5 Mhz */
115 0x4dee, /* 5.12 Mhz */
116 0x0c41, /* 6 Mhz */
117 0x75db, /* 6.144 Mhz */
118 0x1ae6, /* 7.3728 Mhz */
119 0x0600, /* 8 Mhz */
120 0x585b /* 8.192 Mhz */
124 0x3200, /* 1 Mhz */
125 0x1b20, /* 1.8432 Mhz */
126 0x1900, /* 2 Mhz */
127 0xf42b, /* 2.4576 Mhz */
128 0x37e3, /* 3.57954 Mhz */
129 0x1b21, /* 3.6864 Mhz */
130 0x0c80, /* 4 Mhz */
131 0x98ee, /* 4.906 Mhz */
132 0xd5b4, /* 4.9152 Mhz */
133 0x0a00, /* 5 Mhz */
134 0x4e27, /* 5.12 Mhz */
135 0x1902, /* 6 Mhz */
136 0xec1c, /* 6.144 Mhz */
137 0x1b23, /* 7.3728 Mhz */
138 0x0640, /* 8 Mhz */
139 0xb11c /* 8.192 Mhz */
142 #define DID0_VER_MASK 0x70000000
143 #define DID0_VER_0 0x00000000
144 #define DID0_VER_1 0x10000000
146 #define DID0_CLASS_MASK 0x00FF0000
147 #define DID0_CLASS_SANDSTORM 0x00000000
148 #define DID0_CLASS_FURY 0x00010000
177 case 0x000: /* DID0 */ in ssys_read()
179 case 0x004: /* DID1 */ in ssys_read()
181 case 0x008: /* DC0 */ in ssys_read()
183 case 0x010: /* DC1 */ in ssys_read()
185 case 0x014: /* DC2 */ in ssys_read()
187 case 0x018: /* DC3 */ in ssys_read()
189 case 0x01c: /* DC4 */ in ssys_read()
191 case 0x030: /* PBORCTL */ in ssys_read()
193 case 0x034: /* LDOPCTL */ in ssys_read()
195 case 0x040: /* SRCR0 */ in ssys_read()
196 return 0; in ssys_read()
197 case 0x044: /* SRCR1 */ in ssys_read()
198 return 0; in ssys_read()
199 case 0x048: /* SRCR2 */ in ssys_read()
200 return 0; in ssys_read()
201 case 0x050: /* RIS */ in ssys_read()
203 case 0x054: /* IMC */ in ssys_read()
205 case 0x058: /* MISC */ in ssys_read()
207 case 0x05c: /* RESC */ in ssys_read()
209 case 0x060: /* RCC */ in ssys_read()
211 case 0x064: /* PLLCFG */ in ssys_read()
214 xtal = (s->rcc >> 6) & 0xf; in ssys_read()
224 case 0x070: /* RCC2 */ in ssys_read()
226 case 0x100: /* RCGC0 */ in ssys_read()
227 return s->rcgc[0]; in ssys_read()
228 case 0x104: /* RCGC1 */ in ssys_read()
230 case 0x108: /* RCGC2 */ in ssys_read()
232 case 0x110: /* SCGC0 */ in ssys_read()
233 return s->scgc[0]; in ssys_read()
234 case 0x114: /* SCGC1 */ in ssys_read()
236 case 0x118: /* SCGC2 */ in ssys_read()
238 case 0x120: /* DCGC0 */ in ssys_read()
239 return s->dcgc[0]; in ssys_read()
240 case 0x124: /* DCGC1 */ in ssys_read()
242 case 0x128: /* DCGC2 */ in ssys_read()
244 case 0x150: /* CLKVCLR */ in ssys_read()
246 case 0x160: /* LDOARST */ in ssys_read()
248 case 0x1e0: /* USER0 */ in ssys_read()
250 case 0x1e4: /* USER1 */ in ssys_read()
254 "SSYS: read at bad offset 0x%x\n", (int)offset); in ssys_read()
255 return 0; in ssys_read()
261 return (s->rcc2 >> 31) & 0x1; in ssys_use_rcc2()
273 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input in ssys_calculate_system_clock()
278 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); in ssys_calculate_system_clock()
280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); in ssys_calculate_system_clock()
294 case 0x030: /* PBORCTL */ in ssys_write()
295 s->pborctl = value & 0xffff; in ssys_write()
297 case 0x034: /* LDOPCTL */ in ssys_write()
298 s->ldopctl = value & 0x1f; in ssys_write()
300 case 0x040: /* SRCR0 */ in ssys_write()
301 case 0x044: /* SRCR1 */ in ssys_write()
302 case 0x048: /* SRCR2 */ in ssys_write()
305 case 0x054: /* IMC */ in ssys_write()
306 s->int_mask = value & 0x7f; in ssys_write()
308 case 0x058: /* MISC */ in ssys_write()
311 case 0x05c: /* RESC */ in ssys_write()
312 s->resc = value & 0x3f; in ssys_write()
314 case 0x060: /* RCC */ in ssys_write()
315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
322 case 0x070: /* RCC2 */ in ssys_write()
327 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
334 case 0x100: /* RCGC0 */ in ssys_write()
335 s->rcgc[0] = value; in ssys_write()
337 case 0x104: /* RCGC1 */ in ssys_write()
340 case 0x108: /* RCGC2 */ in ssys_write()
343 case 0x110: /* SCGC0 */ in ssys_write()
344 s->scgc[0] = value; in ssys_write()
346 case 0x114: /* SCGC1 */ in ssys_write()
349 case 0x118: /* SCGC2 */ in ssys_write()
352 case 0x120: /* DCGC0 */ in ssys_write()
353 s->dcgc[0] = value; in ssys_write()
355 case 0x124: /* DCGC1 */ in ssys_write()
358 case 0x128: /* DCGC2 */ in ssys_write()
361 case 0x150: /* CLKVCLR */ in ssys_write()
364 case 0x160: /* LDOARST */ in ssys_write()
369 "SSYS: write at bad offset 0x%x\n", (int)offset); in ssys_write()
384 s->pborctl = 0x7ffd; in stellaris_sys_reset_enter()
385 s->rcc = 0x078e3ac0; in stellaris_sys_reset_enter()
388 s->rcc2 = 0; in stellaris_sys_reset_enter()
390 s->rcc2 = 0x07802810; in stellaris_sys_reset_enter()
392 s->rcgc[0] = 1; in stellaris_sys_reset_enter()
393 s->scgc[0] = 1; in stellaris_sys_reset_enter()
394 s->dcgc[0] = 1; in stellaris_sys_reset_enter()
415 return 0; in stellaris_sys_post_load()
442 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
443 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
444 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
445 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
446 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
447 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
448 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
449 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
450 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
459 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); in stellaris_sys_instance_init()
488 #define STELLARIS_I2C_MCS_BUSY 0x01
489 #define STELLARIS_I2C_MCS_ERROR 0x02
490 #define STELLARIS_I2C_MCS_ADRACK 0x04
491 #define STELLARIS_I2C_MCS_DATACK 0x08
492 #define STELLARIS_I2C_MCS_ARBLST 0x10
493 #define STELLARIS_I2C_MCS_IDLE 0x20
494 #define STELLARIS_I2C_MCS_BUSBSY 0x40
502 case 0x00: /* MSA */ in stellaris_i2c_read()
504 case 0x04: /* MCS */ in stellaris_i2c_read()
507 case 0x08: /* MDR */ in stellaris_i2c_read()
509 case 0x0c: /* MTPR */ in stellaris_i2c_read()
511 case 0x10: /* MIMR */ in stellaris_i2c_read()
513 case 0x14: /* MRIS */ in stellaris_i2c_read()
515 case 0x18: /* MMIS */ in stellaris_i2c_read()
517 case 0x20: /* MCR */ in stellaris_i2c_read()
521 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); in stellaris_i2c_read()
522 return 0; in stellaris_i2c_read()
530 level = (s->mris & s->mimr) != 0; in stellaris_i2c_update()
540 case 0x00: /* MSA */ in stellaris_i2c_write()
541 s->msa = value & 0xff; in stellaris_i2c_write()
543 case 0x04: /* MCS */ in stellaris_i2c_write()
544 if ((s->mcr & 0x10) == 0) { in stellaris_i2c_write()
549 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
559 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
583 case 0x08: /* MDR */ in stellaris_i2c_write()
584 s->mdr = value & 0xff; in stellaris_i2c_write()
586 case 0x0c: /* MTPR */ in stellaris_i2c_write()
587 s->mtpr = value & 0xff; in stellaris_i2c_write()
589 case 0x10: /* MIMR */ in stellaris_i2c_write()
592 case 0x1c: /* MICR */ in stellaris_i2c_write()
595 case 0x20: /* MCR */ in stellaris_i2c_write()
600 if (value & 0x20) { in stellaris_i2c_write()
604 s->mcr = value & 0x31; in stellaris_i2c_write()
608 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); in stellaris_i2c_write()
625 s->msa = 0; in stellaris_i2c_reset_hold()
626 s->mcs = 0; in stellaris_i2c_reset_hold()
627 s->mdr = 0; in stellaris_i2c_reset_hold()
629 s->mimr = 0; in stellaris_i2c_reset_hold()
630 s->mris = 0; in stellaris_i2c_reset_hold()
631 s->mcr = 0; in stellaris_i2c_reset_hold()
675 "i2c", 0x1000); in stellaris_i2c_init()
682 #define STELLARIS_ADC_EM_CONTROLLER 0
690 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
691 #define STELLARIS_ADC_FIFO_FULL 0x1000
723 tail = s->fifo[n].state & 0xf; in stellaris_adc_fifo_read()
727 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); in stellaris_adc_fifo_read()
729 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) in stellaris_adc_fifo_read()
742 head = (s->fifo[n].state >> 4) & 0xf; in stellaris_adc_fifo_write()
748 head = (head + 1) & 0xf; in stellaris_adc_fifo_write()
750 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); in stellaris_adc_fifo_write()
751 if ((s->fifo[n].state & 0xf) == head) in stellaris_adc_fifo_write()
760 for (n = 0; n < 4; n++) { in stellaris_adc_update()
761 level = (s->ris & s->im & (1 << n)) != 0; in stellaris_adc_update()
771 for (n = 0; n < 4; n++) { in stellaris_adc_trigger()
772 if ((s->actss & (1 << n)) == 0) { in stellaris_adc_trigger()
776 if (((s->emux >> (n * 4)) & 0xff) != 5) { in stellaris_adc_trigger()
784 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); in stellaris_adc_trigger()
795 for (n = 0; n < 4; n++) { in stellaris_adc_reset_hold()
796 s->ssmux[n] = 0; in stellaris_adc_reset_hold()
797 s->ssctl[n] = 0; in stellaris_adc_reset_hold()
808 if (offset >= 0x40 && offset < 0xc0) { in stellaris_adc_read()
810 n = (offset - 0x40) >> 5; in stellaris_adc_read()
811 switch (offset & 0x1f) { in stellaris_adc_read()
812 case 0x00: /* SSMUX */ in stellaris_adc_read()
814 case 0x04: /* SSCTL */ in stellaris_adc_read()
816 case 0x08: /* SSFIFO */ in stellaris_adc_read()
818 case 0x0c: /* SSFSTAT */ in stellaris_adc_read()
825 case 0x00: /* ACTSS */ in stellaris_adc_read()
827 case 0x04: /* RIS */ in stellaris_adc_read()
829 case 0x08: /* IM */ in stellaris_adc_read()
831 case 0x0c: /* ISC */ in stellaris_adc_read()
833 case 0x10: /* OSTAT */ in stellaris_adc_read()
835 case 0x14: /* EMUX */ in stellaris_adc_read()
837 case 0x18: /* USTAT */ in stellaris_adc_read()
839 case 0x20: /* SSPRI */ in stellaris_adc_read()
841 case 0x30: /* SAC */ in stellaris_adc_read()
845 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); in stellaris_adc_read()
846 return 0; in stellaris_adc_read()
856 if (offset >= 0x40 && offset < 0xc0) { in stellaris_adc_write()
858 n = (offset - 0x40) >> 5; in stellaris_adc_write()
859 switch (offset & 0x1f) { in stellaris_adc_write()
860 case 0x00: /* SSMUX */ in stellaris_adc_write()
861 s->ssmux[n] = value & 0x33333333; in stellaris_adc_write()
863 case 0x04: /* SSCTL */ in stellaris_adc_write()
876 case 0x00: /* ACTSS */ in stellaris_adc_write()
877 s->actss = value & 0xf; in stellaris_adc_write()
879 case 0x08: /* IM */ in stellaris_adc_write()
882 case 0x0c: /* ISC */ in stellaris_adc_write()
885 case 0x10: /* OSTAT */ in stellaris_adc_write()
888 case 0x14: /* EMUX */ in stellaris_adc_write()
891 case 0x18: /* USTAT */ in stellaris_adc_write()
894 case 0x20: /* SSPRI */ in stellaris_adc_write()
897 case 0x28: /* PSSI */ in stellaris_adc_write()
900 case 0x30: /* SAC */ in stellaris_adc_write()
905 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); in stellaris_adc_write()
929 VMSTATE_UINT32(fifo[0].state, StellarisADCState),
930 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
931 VMSTATE_UINT32(ssmux[0], StellarisADCState),
932 VMSTATE_UINT32(ssctl[0], StellarisADCState),
957 for (n = 0; n < 4; n++) { in stellaris_adc_init()
962 "adc", 0x1000); in stellaris_adc_init()
970 0,
971 0x0032000e,
972 0x001f001f, /* dc0 */
973 0x001132bf,
974 0x01071013,
975 0x3f0f01ff,
976 0x0000001f,
980 0x10010002,
981 0x1073402e,
982 0x00ff007f, /* dc0 */
983 0x001133ff,
984 0x030f5317,
985 0x0f0f87ff,
986 0x5000007f,
996 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, in stellaris_init()
997 0x40024000, 0x40025000, 0x40026000}; in stellaris_init()
998 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; in stellaris_init()
1053 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; in stellaris_init()
1062 memory_region_add_subregion(system_memory, 0, flash); in stellaris_init()
1066 memory_region_add_subregion(system_memory, 0x20000000, sram); in stellaris_init()
1087 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16)); in stellaris_init()
1114 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); in stellaris_init()
1115 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); in stellaris_init()
1118 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, in stellaris_init()
1124 adc = qdev_get_gpio_in(dev, 0); in stellaris_init()
1128 for (i = 0; i < 4; i++) { in stellaris_init()
1129 if (board->dc2 & (0x10000 << i)) { in stellaris_init()
1138 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); in stellaris_init()
1139 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); in stellaris_init()
1142 qdev_connect_gpio_out(dev, 0, adc); in stellaris_init()
1154 0, in stellaris_init()
1155 0x40000000u); in stellaris_init()
1157 0, in stellaris_init()
1162 for (i = 0; i < 7; i++) { in stellaris_init()
1167 for (j = 0; j < 8; j++) { in stellaris_init()
1175 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, in stellaris_init()
1179 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); in stellaris_init()
1183 for (i = 0; i < 4; i++) { in stellaris_init()
1192 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); in stellaris_init()
1193 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); in stellaris_init()
1197 dev = sysbus_create_simple("pl022", 0x40008000, in stellaris_init()
1214 * ignores stray 0xff commands that occur when deselecting the SD in stellaris_init()
1267 * or at least to an always-0 line here on the board in stellaris_init()
1273 dinfo = drive_get(IF_SD, 0, 0); in stellaris_init()
1292 gpio_d_splitter, 0, in stellaris_init()
1293 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); in stellaris_init()
1296 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); in stellaris_init()
1297 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); in stellaris_init()
1299 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); in stellaris_init()
1302 qemu_irq_raise(gpio_out[GPIO_D][0]); in stellaris_init()
1317 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); in stellaris_init()
1318 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); in stellaris_init()
1330 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { in stellaris_init()
1336 qdev_connect_gpio_out(gpad, 0, in stellaris_init()
1337 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ in stellaris_init()
1347 for (i = 0; i < 7; i++) { in stellaris_init()
1349 for (j = 0; j < 8; j++) { in stellaris_init()
1360 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); in stellaris_init()
1361 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); in stellaris_init()
1362 create_unimplemented_device("PWM", 0x40028000, 0x1000); in stellaris_init()
1363 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); in stellaris_init()
1364 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); in stellaris_init()
1365 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); in stellaris_init()
1366 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); in stellaris_init()
1367 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); in stellaris_init()
1369 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); in stellaris_init()
1375 stellaris_init(machine, &stellaris_boards[0]); in lm3s811evb_init()