52     uint32_t int_enabled[2];  member
66         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);  in pxa2xx_pic_update()
67         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);  in pxa2xx_pic_update()
73     mask[0] = s->int_pending[0] & s->int_enabled[0];  in pxa2xx_pic_update()
74     mask[1] = s->int_pending[1] & s->int_enabled[1];  in pxa2xx_pic_update()
110     mask[0] = s->int_pending[0] & s->int_enabled[0];  in pxa2xx_pic_highest()
111     mask[1] = s->int_pending[1] & s->int_enabled[1];  in pxa2xx_pic_highest()
144         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];  in pxa2xx_pic_mem_read()
146         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];  in pxa2xx_pic_mem_read()
148         return s->int_enabled[0];  in pxa2xx_pic_mem_read()
150         return s->int_enabled[1];  in pxa2xx_pic_mem_read()
158         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];  in pxa2xx_pic_mem_read()
160         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];  in pxa2xx_pic_mem_read()
186         s->int_enabled[0] = value;  in pxa2xx_pic_mem_write()
189         s->int_enabled[1] = value;  in pxa2xx_pic_mem_write()
281     s->int_enabled[0] = 0;  in pxa2xx_pic_reset_hold()
282     s->int_enabled[1] = 0;  in pxa2xx_pic_reset_hold()
320         VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),