Lines Matching refs:PXA2XX_GPIO_BANKS

22 #define PXA2XX_GPIO_BANKS	4  macro
38     uint32_t ilevel[PXA2XX_GPIO_BANKS];
39     uint32_t olevel[PXA2XX_GPIO_BANKS];
40     uint32_t dir[PXA2XX_GPIO_BANKS];
41     uint32_t rising[PXA2XX_GPIO_BANKS];
42     uint32_t falling[PXA2XX_GPIO_BANKS];
43     uint32_t status[PXA2XX_GPIO_BANKS];
44     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
46     uint32_t prev_level[PXA2XX_GPIO_BANKS];
47     qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
100 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
141     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {  in pxa2xx_gpio_handler_update()
324         VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
325         VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
326         VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
327         VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
328         VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329         VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330         VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
331         VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),