Lines Matching refs:value
62 uint32_t value) in omap_badwidth_write8() argument
64 uint8_t val8 = value; in omap_badwidth_write8()
80 uint32_t value) in omap_badwidth_write16() argument
82 uint16_t val16 = value; in omap_badwidth_write16()
98 uint32_t value) in omap_badwidth_write32() argument
101 cpu_physical_memory_write(addr, &value, 4); in omap_badwidth_write32()
228 uint64_t value, unsigned size) in omap_mpu_timer_write() argument
233 omap_badwidth_write32(opaque, addr, value); in omap_mpu_timer_write()
240 s->enable = (value >> 5) & 1; in omap_mpu_timer_write()
241 s->ptv = (value >> 2) & 7; in omap_mpu_timer_write()
242 s->ar = (value >> 1) & 1; in omap_mpu_timer_write()
243 s->st = value & 1; in omap_mpu_timer_write()
248 s->reset_val = value; in omap_mpu_timer_write()
335 uint64_t value, unsigned size) in omap_wd_timer_write() argument
340 omap_badwidth_write16(opaque, addr, value); in omap_wd_timer_write()
347 s->timer.ptv = (value >> 9) & 7; in omap_wd_timer_write()
348 s->timer.ar = (value >> 8) & 1; in omap_wd_timer_write()
349 s->timer.st = (value >> 7) & 1; in omap_wd_timer_write()
350 s->free = (value >> 1) & 1; in omap_wd_timer_write()
355 s->timer.reset_val = value & 0xffff; in omap_wd_timer_write()
359 if (!s->mode && ((value >> 15) & 1)) in omap_wd_timer_write()
361 s->mode |= (value >> 15) & 1; in omap_wd_timer_write()
363 if ((value & 0xff) == 0xa0) { in omap_wd_timer_write()
375 s->last_wr = value & 0xff; in omap_wd_timer_write()
460 uint64_t value, unsigned size) in omap_os_timer_write() argument
466 omap_badwidth_write32(opaque, addr, value); in omap_os_timer_write()
472 s->timer.reset_val = value & 0x00ffffff; in omap_os_timer_write()
480 s->timer.ar = (value >> 3) & 1; in omap_os_timer_write()
481 s->timer.it_ena = (value >> 2) & 1; in omap_os_timer_write()
482 if (s->timer.st != (value & 1) || (value & 2)) { in omap_os_timer_write()
484 s->timer.enable = value & 1; in omap_os_timer_write()
485 s->timer.st = value & 1; in omap_os_timer_write()
580 uint16_t diff, uint16_t value) in omap_ulpd_clk_update() argument
583 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); in omap_ulpd_clk_update()
585 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); in omap_ulpd_clk_update()
589 uint16_t diff, uint16_t value) in omap_ulpd_req_update() argument
592 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); in omap_ulpd_req_update()
594 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); in omap_ulpd_req_update()
596 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); in omap_ulpd_req_update()
598 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); in omap_ulpd_req_update()
602 uint64_t value, unsigned size) in omap_ulpd_pm_write() argument
611 omap_badwidth_write16(opaque, addr, value); in omap_ulpd_pm_write()
627 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { in omap_ulpd_pm_write()
630 if (value & 1) in omap_ulpd_pm_write()
653 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
667 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
671 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
672 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; in omap_ulpd_pm_write()
673 omap_ulpd_clk_update(s, diff, value); in omap_ulpd_pm_write()
677 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
678 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; in omap_ulpd_pm_write()
679 omap_ulpd_req_update(s, diff, value); in omap_ulpd_pm_write()
687 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
688 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; in omap_ulpd_pm_write()
690 if (value & (1 << 4)) { /* PLL_ENABLE */ in omap_ulpd_pm_write()
691 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ in omap_ulpd_pm_write()
692 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ in omap_ulpd_pm_write()
694 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ in omap_ulpd_pm_write()
710 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
711 s->ulpd_pm_regs[addr >> 2] = value & 0xf; in omap_ulpd_pm_write()
714 (value & (1 << 0)) ? "apll" : "dpll4")); in omap_ulpd_pm_write()
821 uint32_t diff, uint32_t value) in omap_pin_funcmux0_update() argument
826 (~value >> 9) & 1); in omap_pin_funcmux0_update()
829 (value >> 7) & 1); in omap_pin_funcmux0_update()
834 uint32_t diff, uint32_t value) in omap_pin_funcmux1_update() argument
839 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); in omap_pin_funcmux1_update()
843 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); in omap_pin_funcmux1_update()
849 uint32_t diff, uint32_t value) in omap_pin_modconf1_update() argument
854 omap_findclk(s, ((value >> 31) & 1) ? in omap_pin_modconf1_update()
859 omap_findclk(s, ((value >> 30) & 1) ? in omap_pin_modconf1_update()
863 omap_findclk(s, ((value >> 29) & 1) ? in omap_pin_modconf1_update()
867 omap_findclk(s, ((value >> 23) & 1) ? in omap_pin_modconf1_update()
871 omap_findclk(s, ((value >> 12) & 1) ? in omap_pin_modconf1_update()
874 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); in omap_pin_modconf1_update()
878 uint64_t value, unsigned size) in omap_pin_cfg_write() argument
884 omap_badwidth_write32(opaque, addr, value); in omap_pin_cfg_write()
890 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
891 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
892 omap_pin_funcmux0_update(s, diff, value); in omap_pin_cfg_write()
896 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
897 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
898 omap_pin_funcmux1_update(s, diff, value); in omap_pin_cfg_write()
902 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
906 s->comp_mode_ctrl[0] = value; in omap_pin_cfg_write()
907 s->compat1509 = (value != 0x0000eaef); in omap_pin_cfg_write()
923 s->func_mux_ctrl[(addr >> 2) - 1] = value; in omap_pin_cfg_write()
930 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; in omap_pin_cfg_write()
934 s->gate_inh_ctrl[0] = value; in omap_pin_cfg_write()
938 s->voltage_ctrl[0] = value; in omap_pin_cfg_write()
942 s->test_dbg_ctrl[0] = value; in omap_pin_cfg_write()
946 diff = s->mod_conf_ctrl[0] ^ value; in omap_pin_cfg_write()
947 s->mod_conf_ctrl[0] = value; in omap_pin_cfg_write()
948 omap_pin_modconf1_update(s, diff, value); in omap_pin_cfg_write()
1037 uint64_t value, unsigned size) in omap_id_write() argument
1040 omap_badwidth_write32(opaque, addr, value); in omap_id_write()
1105 uint64_t value, unsigned size) in omap_mpui_write() argument
1110 omap_badwidth_write32(opaque, addr, value); in omap_mpui_write()
1116 s->mpui_ctrl = value & 0x007fffff; in omap_mpui_write()
1200 uint64_t value, unsigned size) in omap_tipb_bridge_write() argument
1205 omap_badwidth_write16(opaque, addr, value); in omap_tipb_bridge_write()
1211 s->control = value & 0xffff; in omap_tipb_bridge_write()
1215 s->alloc = value & 0x003f; in omap_tipb_bridge_write()
1219 s->buffer = value & 0x0003; in omap_tipb_bridge_write()
1223 s->width_intr = !(value & 2); in omap_tipb_bridge_write()
1224 s->enh_control = value & 0x000f; in omap_tipb_bridge_write()
1309 uint64_t value, unsigned size) in omap_tcmi_write() argument
1314 omap_badwidth_write32(opaque, addr, value); in omap_tcmi_write()
1333 s->tcmi_regs[addr >> 2] = value; in omap_tcmi_write()
1336 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); in omap_tcmi_write()
1402 uint64_t value, unsigned size) in omap_dpll_write() argument
1410 omap_badwidth_write16(opaque, addr, value); in omap_dpll_write()
1416 diff = s->mode & value; in omap_dpll_write()
1417 s->mode = value & 0x2fff; in omap_dpll_write()
1419 if (value & (1 << 4)) { /* PLL_ENABLE */ in omap_dpll_write()
1420 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ in omap_dpll_write()
1421 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ in omap_dpll_write()
1423 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ in omap_dpll_write()
1508 uint16_t diff, uint16_t value) in omap_clkm_ckctl_update() argument
1513 if (value & (1 << 14)) in omap_clkm_ckctl_update()
1522 if (value & (1 << 12)) in omap_clkm_ckctl_update()
1530 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); in omap_clkm_ckctl_update()
1534 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); in omap_clkm_ckctl_update()
1538 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); in omap_clkm_ckctl_update()
1542 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); in omap_clkm_ckctl_update()
1546 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); in omap_clkm_ckctl_update()
1550 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); in omap_clkm_ckctl_update()
1555 uint16_t diff, uint16_t value) in omap_clkm_idlect1_update() argument
1559 if (value & (1 << 11)) { /* SETARM_IDLE */ in omap_clkm_idlect1_update()
1562 if (!(value & (1 << 10))) { /* WKUP_MODE */ in omap_clkm_idlect1_update()
1570 omap_clk_canidle(clk, (value >> bit) & 1); \ in omap_clkm_idlect1_update()
1589 uint16_t diff, uint16_t value) in omap_clkm_idlect2_update() argument
1596 omap_clk_onoff(clk, (value >> bit) & 1); \ in omap_clkm_idlect2_update()
1612 uint16_t diff, uint16_t value) in omap_clkm_ckout1_update() argument
1618 switch ((value >> 4) & 3) { in omap_clkm_ckout1_update()
1633 switch ((value >> 2) & 3) { in omap_clkm_ckout1_update()
1650 switch ((value >> 0) & 3) { in omap_clkm_ckout1_update()
1670 uint64_t value, unsigned size) in omap_clkm_write() argument
1681 omap_badwidth_write16(opaque, addr, value); in omap_clkm_write()
1687 diff = s->clkm.arm_ckctl ^ value; in omap_clkm_write()
1688 s->clkm.arm_ckctl = value & 0x7fff; in omap_clkm_write()
1689 omap_clkm_ckctl_update(s, diff, value); in omap_clkm_write()
1693 diff = s->clkm.arm_idlect1 ^ value; in omap_clkm_write()
1694 s->clkm.arm_idlect1 = value & 0x0fff; in omap_clkm_write()
1695 omap_clkm_idlect1_update(s, diff, value); in omap_clkm_write()
1699 diff = s->clkm.arm_idlect2 ^ value; in omap_clkm_write()
1700 s->clkm.arm_idlect2 = value & 0x07ff; in omap_clkm_write()
1701 omap_clkm_idlect2_update(s, diff, value); in omap_clkm_write()
1705 s->clkm.arm_ewupct = value & 0x003f; in omap_clkm_write()
1709 diff = s->clkm.arm_rstct1 ^ value; in omap_clkm_write()
1710 s->clkm.arm_rstct1 = value & 0x0007; in omap_clkm_write()
1711 if (value & 9) { in omap_clkm_write()
1715 if (diff & ~value & 4) { /* DSP_RST */ in omap_clkm_write()
1722 omap_clk_canidle(clk, (~value >> 1) & 1); in omap_clkm_write()
1727 s->clkm.arm_rstct2 = value & 0x0001; in omap_clkm_write()
1731 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { in omap_clkm_write()
1732 s->clkm.clocking_scheme = (value >> 11) & 7; in omap_clkm_write()
1736 s->clkm.cold_start &= value & 0x3f; in omap_clkm_write()
1740 diff = s->clkm.arm_ckout1 ^ value; in omap_clkm_write()
1741 s->clkm.arm_ckout1 = value & 0x003f; in omap_clkm_write()
1742 omap_clkm_ckout1_update(s, diff, value); in omap_clkm_write()
1787 uint16_t diff, uint16_t value) in omap_clkdsp_idlect1_update() argument
1795 uint16_t diff, uint16_t value) in omap_clkdsp_idlect2_update() argument
1803 uint64_t value, unsigned size) in omap_clkdsp_write() argument
1809 omap_badwidth_write16(opaque, addr, value); in omap_clkdsp_write()
1815 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1816 s->clkm.dsp_idlect1 = value & 0x01f7; in omap_clkdsp_write()
1817 omap_clkdsp_idlect1_update(s, diff, value); in omap_clkdsp_write()
1821 s->clkm.dsp_idlect2 = value & 0x0037; in omap_clkdsp_write()
1822 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1823 omap_clkdsp_idlect2_update(s, diff, value); in omap_clkdsp_write()
1827 s->clkm.dsp_rstct2 = value & 0x0001; in omap_clkdsp_write()
1831 s->clkm.cold_start &= value & 0x3f; in omap_clkdsp_write()
2009 uint64_t value, unsigned size) in omap_mpuio_write() argument
2017 omap_badwidth_write16(opaque, addr, value); in omap_mpuio_write()
2023 diff = (s->outputs ^ value) & ~s->dir; in omap_mpuio_write()
2024 s->outputs = value; in omap_mpuio_write()
2027 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2033 diff = s->outputs & (s->dir ^ value); in omap_mpuio_write()
2034 s->dir = value; in omap_mpuio_write()
2036 value = s->outputs & ~s->dir; in omap_mpuio_write()
2039 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2045 s->cols = value; in omap_mpuio_write()
2050 s->event = value & 0x1f; in omap_mpuio_write()
2054 s->edge = value; in omap_mpuio_write()
2058 s->kbd_mask = value & 1; in omap_mpuio_write()
2063 s->mask = value; in omap_mpuio_write()
2067 s->debounce = value & 0x1ff; in omap_mpuio_write()
2236 uint64_t value, unsigned size) in omap_uwire_write() argument
2242 omap_badwidth_write16(opaque, addr, value); in omap_uwire_write()
2248 s->txbuf = value; /* TD */ in omap_uwire_write()
2258 s->control = value & 0x1fff; in omap_uwire_write()
2259 if (value & (1 << 13)) /* START */ in omap_uwire_write()
2264 s->setup[0] = value & 0x003f; in omap_uwire_write()
2268 s->setup[1] = value & 0x0fc0; in omap_uwire_write()
2272 s->setup[2] = value & 0x0003; in omap_uwire_write()
2276 s->setup[3] = value & 0x0001; in omap_uwire_write()
2280 s->setup[4] = value & 0x000f; in omap_uwire_write()
2374 uint64_t value, unsigned size) in omap_pwl_write() argument
2380 omap_badwidth_write8(opaque, addr, value); in omap_pwl_write()
2386 s->level = value; in omap_pwl_write()
2390 s->enable = value & 1; in omap_pwl_write()
2469 uint64_t value, unsigned size) in omap_pwt_write() argument
2475 omap_badwidth_write8(opaque, addr, value); in omap_pwt_write()
2481 s->frc = value & 0x3f; in omap_pwt_write()
2484 if ((value ^ s->vrc) & 1) { in omap_pwt_write()
2485 if (value & 1) in omap_pwt_write()
2492 (2 << (value & 3)) * in omap_pwt_write()
2494 ((value & (1 << 2)) ? 101 : 107) * in omap_pwt_write()
2496 ((value & (1 << 3)) ? 49 : 55) * in omap_pwt_write()
2498 ((value & (1 << 4)) ? 50 : 63) * in omap_pwt_write()
2500 ((value & (1 << 5)) ? 80 : 127) / in omap_pwt_write()
2505 s->vrc = value & 0x7f; in omap_pwt_write()
2508 s->gcr = value & 3; in omap_pwt_write()
2660 uint64_t value, unsigned size) in omap_rtc_write() argument
2668 omap_badwidth_write8(opaque, addr, value); in omap_rtc_write()
2675 printf("RTC SEC_REG <-- %02x\n", value); in omap_rtc_write()
2678 s->ti += from_bcd(value); in omap_rtc_write()
2683 printf("RTC MIN_REG <-- %02x\n", value); in omap_rtc_write()
2686 s->ti += from_bcd(value) * 60; in omap_rtc_write()
2691 printf("RTC HRS_REG <-- %02x\n", value); in omap_rtc_write()
2695 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; in omap_rtc_write()
2696 s->ti += ((value >> 7) & 1) * 43200; in omap_rtc_write()
2698 s->ti += from_bcd(value & 0x3f) * 3600; in omap_rtc_write()
2703 printf("RTC DAY_REG <-- %02x\n", value); in omap_rtc_write()
2706 s->ti += from_bcd(value) * 86400; in omap_rtc_write()
2711 printf("RTC MTH_REG <-- %02x\n", value); in omap_rtc_write()
2714 new_tm.tm_mon = from_bcd(value); in omap_rtc_write()
2724 s->ti += from_bcd(value) * 2592000; in omap_rtc_write()
2730 printf("RTC YRS_REG <-- %02x\n", value); in omap_rtc_write()
2733 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); in omap_rtc_write()
2743 s->ti += (time_t)from_bcd(value) * 31536000; in omap_rtc_write()
2752 printf("ALM SEC_REG <-- %02x\n", value); in omap_rtc_write()
2754 s->alarm_tm.tm_sec = from_bcd(value); in omap_rtc_write()
2760 printf("ALM MIN_REG <-- %02x\n", value); in omap_rtc_write()
2762 s->alarm_tm.tm_min = from_bcd(value); in omap_rtc_write()
2768 printf("ALM HRS_REG <-- %02x\n", value); in omap_rtc_write()
2772 ((from_bcd(value & 0x3f)) % 12) + in omap_rtc_write()
2773 ((value >> 7) & 1) * 12; in omap_rtc_write()
2775 s->alarm_tm.tm_hour = from_bcd(value); in omap_rtc_write()
2781 printf("ALM DAY_REG <-- %02x\n", value); in omap_rtc_write()
2783 s->alarm_tm.tm_mday = from_bcd(value); in omap_rtc_write()
2789 printf("ALM MON_REG <-- %02x\n", value); in omap_rtc_write()
2791 s->alarm_tm.tm_mon = from_bcd(value); in omap_rtc_write()
2797 printf("ALM YRS_REG <-- %02x\n", value); in omap_rtc_write()
2799 s->alarm_tm.tm_year = from_bcd(value); in omap_rtc_write()
2805 printf("RTC CONTROL <-- %02x\n", value); in omap_rtc_write()
2807 s->pm_am = (value >> 3) & 1; in omap_rtc_write()
2808 s->auto_comp = (value >> 2) & 1; in omap_rtc_write()
2809 s->round = (value >> 1) & 1; in omap_rtc_write()
2810 s->running = value & 1; in omap_rtc_write()
2817 printf("RTC STATUSL <-- %02x\n", value); in omap_rtc_write()
2819 s->status &= ~((value & 0xc0) ^ 0x80); in omap_rtc_write()
2825 printf("RTC INTRS <-- %02x\n", value); in omap_rtc_write()
2827 s->interrupts = value; in omap_rtc_write()
2832 printf("RTC COMPLSB <-- %02x\n", value); in omap_rtc_write()
2835 s->comp_reg |= 0x00ff & value; in omap_rtc_write()
2840 printf("RTC COMPMSB <-- %02x\n", value); in omap_rtc_write()
2843 s->comp_reg |= 0xff00 & (value << 8); in omap_rtc_write()
3269 uint32_t value) in omap_mcbsp_writeh() argument
3288 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; in omap_mcbsp_writeh()
3289 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; in omap_mcbsp_writeh()
3299 s->spcr[1] |= 0x03f9 & value; in omap_mcbsp_writeh()
3300 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ in omap_mcbsp_writeh()
3301 if (~value & 1) /* XRST */ in omap_mcbsp_writeh()
3307 s->spcr[0] |= 0xf8f9 & value; in omap_mcbsp_writeh()
3308 if (value & (1 << 15)) /* DLB */ in omap_mcbsp_writeh()
3310 if (~value & 1) { /* RRST */ in omap_mcbsp_writeh()
3319 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3322 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3325 s->xcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3328 s->xcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3331 s->srgr[1] = value & 0xffff; in omap_mcbsp_writeh()
3335 s->srgr[0] = value & 0xffff; in omap_mcbsp_writeh()
3339 s->mcr[1] = value & 0x03e3; in omap_mcbsp_writeh()
3340 if (value & 3) /* XMCM */ in omap_mcbsp_writeh()
3344 s->mcr[0] = value & 0x03e1; in omap_mcbsp_writeh()
3345 if (value & 1) /* RMCM */ in omap_mcbsp_writeh()
3349 s->rcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3352 s->rcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3355 s->xcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3358 s->xcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3361 s->pcr = value & 0x7faf; in omap_mcbsp_writeh()
3364 s->rcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3367 s->rcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3370 s->xcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3373 s->xcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3376 s->rcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3379 s->rcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3382 s->xcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3385 s->xcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3388 s->rcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3391 s->rcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3394 s->xcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3397 s->xcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3405 uint32_t value) in omap_mcbsp_writew() argument
3417 (value >> 24) & 0xff; in omap_mcbsp_writew()
3419 (value >> 16) & 0xff; in omap_mcbsp_writew()
3421 (value >> 8) & 0xff; in omap_mcbsp_writew()
3423 (value >> 0) & 0xff; in omap_mcbsp_writew()
3432 omap_badwidth_write16(opaque, addr, value); in omap_mcbsp_writew()
3436 uint64_t value, unsigned size) in omap_mcbsp_write() argument
3440 omap_mcbsp_writeh(opaque, addr, value); in omap_mcbsp_write()
3443 omap_mcbsp_writew(opaque, addr, value); in omap_mcbsp_write()
3446 omap_badwidth_write16(opaque, addr, value); in omap_mcbsp_write()
3612 uint64_t value, unsigned size) in omap_lpg_write() argument
3618 omap_badwidth_write8(opaque, addr, value); in omap_lpg_write()
3624 if (~value & (1 << 6)) /* LPGRES */ in omap_lpg_write()
3626 s->control = value & 0xff; in omap_lpg_write()
3631 s->power = value & 0x01; in omap_lpg_write()
3688 uint64_t value, unsigned size) in omap_mpui_io_write() argument
3691 omap_badwidth_write16(opaque, addr, value); in omap_mpui_io_write()