Lines Matching +full:- +full:s
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
26 #include "exec/address-spaces.h"
29 #include "hw/qdev-properties.h"
43 #include "target/arm/cpu-qom.h"
47 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
125 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; in omap_timer_read()
127 if (timer->st && timer->enable && timer->rate) in omap_timer_read()
128 return timer->val - muldiv64(distance >> (timer->ptv + 1), in omap_timer_read()
129 timer->rate, NANOSECONDS_PER_SECOND); in omap_timer_read()
131 return timer->val; in omap_timer_read()
136 timer->val = omap_timer_read(timer); in omap_timer_sync()
137 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in omap_timer_sync()
144 if (timer->enable && timer->st && timer->rate) { in omap_timer_update()
145 timer->val = timer->reset_val; /* Should skip this on clk enable */ in omap_timer_update()
146 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), in omap_timer_update()
147 NANOSECONDS_PER_SECOND, timer->rate); in omap_timer_update()
150 * auto-reload isn't set, then fire immediately. This is a hack in omap_timer_update()
155 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) { in omap_timer_update()
156 timer_mod(timer->timer, timer->time + expires); in omap_timer_update()
158 qemu_bh_schedule(timer->tick); in omap_timer_update()
161 timer_del(timer->timer); in omap_timer_update()
168 if (!timer->ar) { in omap_timer_fire()
169 timer->val = 0; in omap_timer_fire()
170 timer->st = 0; in omap_timer_fire()
173 if (timer->it_ena) in omap_timer_fire()
174 /* Edge-triggered irq */ in omap_timer_fire()
175 qemu_irq_pulse(timer->irq); in omap_timer_fire()
192 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; in omap_timer_clk_update()
198 omap_clk_adduser(timer->clk, in omap_timer_clk_setup()
200 timer->rate = omap_clk_getrate(timer->clk); in omap_timer_clk_setup()
206 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_read() local
214 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; in omap_mpu_timer_read()
220 return omap_timer_read(s); in omap_mpu_timer_read()
230 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_write() local
239 omap_timer_sync(s); in omap_mpu_timer_write()
240 s->enable = (value >> 5) & 1; in omap_mpu_timer_write()
241 s->ptv = (value >> 2) & 7; in omap_mpu_timer_write()
242 s->ar = (value >> 1) & 1; in omap_mpu_timer_write()
243 s->st = value & 1; in omap_mpu_timer_write()
244 omap_timer_update(s); in omap_mpu_timer_write()
248 s->reset_val = value; in omap_mpu_timer_write()
266 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) in omap_mpu_timer_reset() argument
268 timer_del(s->timer); in omap_mpu_timer_reset()
269 s->enable = 0; in omap_mpu_timer_reset()
270 s->reset_val = 31337; in omap_mpu_timer_reset()
271 s->val = 0; in omap_mpu_timer_reset()
272 s->ptv = 0; in omap_mpu_timer_reset()
273 s->ar = 0; in omap_mpu_timer_reset()
274 s->st = 0; in omap_mpu_timer_reset()
275 s->it_ena = 1; in omap_mpu_timer_reset()
282 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); in omap_mpu_timer_init() local
284 s->irq = irq; in omap_mpu_timer_init()
285 s->clk = clk; in omap_mpu_timer_init()
286 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); in omap_mpu_timer_init()
287 s->tick = qemu_bh_new(omap_timer_fire, s); in omap_mpu_timer_init()
288 omap_mpu_timer_reset(s); in omap_mpu_timer_init()
289 omap_timer_clk_setup(s); in omap_mpu_timer_init()
291 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, in omap_mpu_timer_init()
292 "omap-mpu-timer", 0x100); in omap_mpu_timer_init()
294 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_mpu_timer_init()
296 return s; in omap_mpu_timer_init()
312 struct omap_watchdog_timer_s *s = opaque; in omap_wd_timer_read() local
320 return (s->timer.ptv << 9) | (s->timer.ar << 8) | in omap_wd_timer_read()
321 (s->timer.st << 7) | (s->free << 1); in omap_wd_timer_read()
324 return omap_timer_read(&s->timer); in omap_wd_timer_read()
327 return s->mode << 15; in omap_wd_timer_read()
337 struct omap_watchdog_timer_s *s = opaque; in omap_wd_timer_write() local
346 omap_timer_sync(&s->timer); in omap_wd_timer_write()
347 s->timer.ptv = (value >> 9) & 7; in omap_wd_timer_write()
348 s->timer.ar = (value >> 8) & 1; in omap_wd_timer_write()
349 s->timer.st = (value >> 7) & 1; in omap_wd_timer_write()
350 s->free = (value >> 1) & 1; in omap_wd_timer_write()
351 omap_timer_update(&s->timer); in omap_wd_timer_write()
355 s->timer.reset_val = value & 0xffff; in omap_wd_timer_write()
359 if (!s->mode && ((value >> 15) & 1)) in omap_wd_timer_write()
360 omap_clk_get(s->timer.clk); in omap_wd_timer_write()
361 s->mode |= (value >> 15) & 1; in omap_wd_timer_write()
362 if (s->last_wr == 0xf5) { in omap_wd_timer_write()
364 if (s->mode) { in omap_wd_timer_write()
365 s->mode = 0; in omap_wd_timer_write()
366 omap_clk_put(s->timer.clk); in omap_wd_timer_write()
371 s->reset = 1; in omap_wd_timer_write()
375 s->last_wr = value & 0xff; in omap_wd_timer_write()
389 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) in omap_wd_timer_reset() argument
391 timer_del(s->timer.timer); in omap_wd_timer_reset()
392 if (!s->mode) in omap_wd_timer_reset()
393 omap_clk_get(s->timer.clk); in omap_wd_timer_reset()
394 s->mode = 1; in omap_wd_timer_reset()
395 s->free = 1; in omap_wd_timer_reset()
396 s->reset = 0; in omap_wd_timer_reset()
397 s->timer.enable = 1; in omap_wd_timer_reset()
398 s->timer.it_ena = 1; in omap_wd_timer_reset()
399 s->timer.reset_val = 0xffff; in omap_wd_timer_reset()
400 s->timer.val = 0; in omap_wd_timer_reset()
401 s->timer.st = 0; in omap_wd_timer_reset()
402 s->timer.ptv = 0; in omap_wd_timer_reset()
403 s->timer.ar = 0; in omap_wd_timer_reset()
404 omap_timer_update(&s->timer); in omap_wd_timer_reset()
411 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); in omap_wd_timer_init() local
413 s->timer.irq = irq; in omap_wd_timer_init()
414 s->timer.clk = clk; in omap_wd_timer_init()
415 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); in omap_wd_timer_init()
416 omap_wd_timer_reset(s); in omap_wd_timer_init()
417 omap_timer_clk_setup(&s->timer); in omap_wd_timer_init()
419 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, in omap_wd_timer_init()
420 "omap-wd-timer", 0x100); in omap_wd_timer_init()
421 memory_region_add_subregion(memory, base, &s->iomem); in omap_wd_timer_init()
423 return s; in omap_wd_timer_init()
426 /* 32-kHz timer */
435 struct omap_32khz_timer_s *s = opaque; in omap_os_timer_read() local
444 return s->timer.reset_val; in omap_os_timer_read()
447 return omap_timer_read(&s->timer); in omap_os_timer_read()
450 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; in omap_os_timer_read()
462 struct omap_32khz_timer_s *s = opaque; in omap_os_timer_write() local
472 s->timer.reset_val = value & 0x00ffffff; in omap_os_timer_write()
480 s->timer.ar = (value >> 3) & 1; in omap_os_timer_write()
481 s->timer.it_ena = (value >> 2) & 1; in omap_os_timer_write()
482 if (s->timer.st != (value & 1) || (value & 2)) { in omap_os_timer_write()
483 omap_timer_sync(&s->timer); in omap_os_timer_write()
484 s->timer.enable = value & 1; in omap_os_timer_write()
485 s->timer.st = value & 1; in omap_os_timer_write()
486 omap_timer_update(&s->timer); in omap_os_timer_write()
501 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) in omap_os_timer_reset() argument
503 timer_del(s->timer.timer); in omap_os_timer_reset()
504 s->timer.enable = 0; in omap_os_timer_reset()
505 s->timer.it_ena = 0; in omap_os_timer_reset()
506 s->timer.reset_val = 0x00ffffff; in omap_os_timer_reset()
507 s->timer.val = 0; in omap_os_timer_reset()
508 s->timer.st = 0; in omap_os_timer_reset()
509 s->timer.ptv = 0; in omap_os_timer_reset()
510 s->timer.ar = 1; in omap_os_timer_reset()
517 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); in omap_os_timer_init() local
519 s->timer.irq = irq; in omap_os_timer_init()
520 s->timer.clk = clk; in omap_os_timer_init()
521 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); in omap_os_timer_init()
522 omap_os_timer_reset(s); in omap_os_timer_init()
523 omap_timer_clk_setup(&s->timer); in omap_os_timer_init()
525 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, in omap_os_timer_init()
526 "omap-os-timer", 0x800); in omap_os_timer_init()
527 memory_region_add_subregion(memory, base, &s->iomem); in omap_os_timer_init()
529 return s; in omap_os_timer_init()
532 /* Ultra Low-Power Device Module */
536 struct omap_mpu_state_s *s = opaque; in omap_ulpd_pm_read() local
545 ret = s->ulpd_pm_regs[addr >> 2]; in omap_ulpd_pm_read()
546 s->ulpd_pm_regs[addr >> 2] = 0; in omap_ulpd_pm_read()
547 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); in omap_ulpd_pm_read()
572 return s->ulpd_pm_regs[addr >> 2]; in omap_ulpd_pm_read()
579 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, in omap_ulpd_clk_update() argument
583 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); in omap_ulpd_clk_update()
585 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); in omap_ulpd_clk_update()
588 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, in omap_ulpd_req_update() argument
592 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); in omap_ulpd_req_update()
594 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); in omap_ulpd_req_update()
596 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); in omap_ulpd_req_update()
598 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); in omap_ulpd_req_update()
604 struct omap_mpu_state_s *s = opaque; in omap_ulpd_pm_write() local
627 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { in omap_ulpd_pm_write()
631 s->ulpd_gauge_start = now; in omap_ulpd_pm_write()
633 now -= s->ulpd_gauge_start; in omap_ulpd_pm_write()
635 /* 32-kHz ticks */ in omap_ulpd_pm_write()
637 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
638 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
640 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; in omap_ulpd_pm_write()
644 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
645 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
647 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; in omap_ulpd_pm_write()
649 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ in omap_ulpd_pm_write()
650 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); in omap_ulpd_pm_write()
653 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
667 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
671 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
672 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; in omap_ulpd_pm_write()
673 omap_ulpd_clk_update(s, diff, value); in omap_ulpd_pm_write()
677 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
678 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; in omap_ulpd_pm_write()
679 omap_ulpd_req_update(s, diff, value); in omap_ulpd_pm_write()
687 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
688 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; in omap_ulpd_pm_write()
697 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); in omap_ulpd_pm_write()
701 s->ulpd_pm_regs[addr >> 2] = in omap_ulpd_pm_write()
702 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | in omap_ulpd_pm_write()
703 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); in omap_ulpd_pm_write()
706 s->ulpd_pm_regs[addr >> 2] |= 2; in omap_ulpd_pm_write()
710 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
711 s->ulpd_pm_regs[addr >> 2] = value & 0xf; in omap_ulpd_pm_write()
713 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, in omap_ulpd_pm_write()
730 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; in omap_ulpd_pm_reset()
731 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; in omap_ulpd_pm_reset()
732 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; in omap_ulpd_pm_reset()
733 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; in omap_ulpd_pm_reset()
734 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; in omap_ulpd_pm_reset()
735 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; in omap_ulpd_pm_reset()
736 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; in omap_ulpd_pm_reset()
737 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; in omap_ulpd_pm_reset()
738 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; in omap_ulpd_pm_reset()
739 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; in omap_ulpd_pm_reset()
740 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; in omap_ulpd_pm_reset()
741 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); in omap_ulpd_pm_reset()
742 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; in omap_ulpd_pm_reset()
743 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); in omap_ulpd_pm_reset()
744 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; in omap_ulpd_pm_reset()
745 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; in omap_ulpd_pm_reset()
746 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; in omap_ulpd_pm_reset()
747 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ in omap_ulpd_pm_reset()
748 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; in omap_ulpd_pm_reset()
749 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; in omap_ulpd_pm_reset()
750 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; in omap_ulpd_pm_reset()
759 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, in omap_ulpd_pm_init()
760 "omap-ulpd-pm", 0x800); in omap_ulpd_pm_init()
761 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); in omap_ulpd_pm_init()
769 struct omap_mpu_state_s *s = opaque; in omap_pin_cfg_read() local
779 return s->func_mux_ctrl[addr >> 2]; in omap_pin_cfg_read()
782 return s->comp_mode_ctrl[0]; in omap_pin_cfg_read()
795 return s->func_mux_ctrl[(addr >> 2) - 1]; in omap_pin_cfg_read()
801 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; in omap_pin_cfg_read()
804 return s->gate_inh_ctrl[0]; in omap_pin_cfg_read()
807 return s->voltage_ctrl[0]; in omap_pin_cfg_read()
810 return s->test_dbg_ctrl[0]; in omap_pin_cfg_read()
813 return s->mod_conf_ctrl[0]; in omap_pin_cfg_read()
820 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, in omap_pin_funcmux0_update() argument
823 if (s->compat1509) { in omap_pin_funcmux0_update()
825 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), in omap_pin_funcmux0_update()
828 omap_clk_onoff(omap_findclk(s, "usb.clko"), in omap_pin_funcmux0_update()
833 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, in omap_pin_funcmux1_update() argument
836 if (s->compat1509) { in omap_pin_funcmux1_update()
839 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); in omap_pin_funcmux1_update()
843 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); in omap_pin_funcmux1_update()
848 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, in omap_pin_modconf1_update() argument
853 omap_clk_reparent(omap_findclk(s, "uart3_ck"), in omap_pin_modconf1_update()
854 omap_findclk(s, ((value >> 31) & 1) ? in omap_pin_modconf1_update()
858 omap_clk_reparent(omap_findclk(s, "uart2_ck"), in omap_pin_modconf1_update()
859 omap_findclk(s, ((value >> 30) & 1) ? in omap_pin_modconf1_update()
862 omap_clk_reparent(omap_findclk(s, "uart1_ck"), in omap_pin_modconf1_update()
863 omap_findclk(s, ((value >> 29) & 1) ? in omap_pin_modconf1_update()
866 omap_clk_reparent(omap_findclk(s, "mmc_ck"), in omap_pin_modconf1_update()
867 omap_findclk(s, ((value >> 23) & 1) ? in omap_pin_modconf1_update()
870 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), in omap_pin_modconf1_update()
871 omap_findclk(s, ((value >> 12) & 1) ? in omap_pin_modconf1_update()
874 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); in omap_pin_modconf1_update()
880 struct omap_mpu_state_s *s = opaque; in omap_pin_cfg_write() local
890 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
891 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
892 omap_pin_funcmux0_update(s, diff, value); in omap_pin_cfg_write()
896 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
897 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
898 omap_pin_funcmux1_update(s, diff, value); in omap_pin_cfg_write()
902 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
906 s->comp_mode_ctrl[0] = value; in omap_pin_cfg_write()
907 s->compat1509 = (value != 0x0000eaef); in omap_pin_cfg_write()
908 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); in omap_pin_cfg_write()
909 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); in omap_pin_cfg_write()
923 s->func_mux_ctrl[(addr >> 2) - 1] = value; in omap_pin_cfg_write()
930 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; in omap_pin_cfg_write()
934 s->gate_inh_ctrl[0] = value; in omap_pin_cfg_write()
938 s->voltage_ctrl[0] = value; in omap_pin_cfg_write()
942 s->test_dbg_ctrl[0] = value; in omap_pin_cfg_write()
946 diff = s->mod_conf_ctrl[0] ^ value; in omap_pin_cfg_write()
947 s->mod_conf_ctrl[0] = value; in omap_pin_cfg_write()
948 omap_pin_modconf1_update(s, diff, value); in omap_pin_cfg_write()
965 mpu->compat1509 = 1; in omap_pin_cfg_reset()
966 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); in omap_pin_cfg_reset()
967 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); in omap_pin_cfg_reset()
968 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); in omap_pin_cfg_reset()
969 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); in omap_pin_cfg_reset()
970 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); in omap_pin_cfg_reset()
971 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); in omap_pin_cfg_reset()
972 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); in omap_pin_cfg_reset()
973 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); in omap_pin_cfg_reset()
974 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); in omap_pin_cfg_reset()
975 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); in omap_pin_cfg_reset()
982 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, in omap_pin_cfg_init()
983 "omap-pin-cfg", 0x800); in omap_pin_cfg_init()
984 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); in omap_pin_cfg_init()
992 struct omap_mpu_state_s *s = opaque; in omap_id_read() local
1010 switch (s->mpu_model) { in omap_id_read()
1016 hw_error("%s: bad mpu model\n", __func__); in omap_id_read()
1021 switch (s->mpu_model) { in omap_id_read()
1027 hw_error("%s: bad mpu model\n", __func__); in omap_id_read()
1055 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, in omap_id_init()
1056 "omap-id", 0x100000000ULL); in omap_id_init()
1057 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, in omap_id_init()
1059 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); in omap_id_init()
1060 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, in omap_id_init()
1062 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); in omap_id_init()
1064 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", in omap_id_init()
1065 &mpu->id_iomem, 0xfffe2000, 0x800); in omap_id_init()
1066 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); in omap_id_init()
1074 struct omap_mpu_state_s *s = opaque; in omap_mpui_read() local
1082 return s->mpui_ctrl; in omap_mpui_read()
1107 struct omap_mpu_state_s *s = opaque; in omap_mpui_write() local
1116 s->mpui_ctrl = value & 0x007fffff; in omap_mpui_write()
1142 static void omap_mpui_reset(struct omap_mpu_state_s *s) in omap_mpui_reset() argument
1144 s->mpui_ctrl = 0x0003ff1b; in omap_mpui_reset()
1150 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, in omap_mpui_init()
1151 "omap-mpui", 0x100); in omap_mpui_init()
1152 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); in omap_mpui_init()
1172 struct omap_tipb_bridge_s *s = opaque; in omap_tipb_bridge_read() local
1180 return s->control; in omap_tipb_bridge_read()
1182 return s->alloc; in omap_tipb_bridge_read()
1184 return s->buffer; in omap_tipb_bridge_read()
1186 return s->enh_control; in omap_tipb_bridge_read()
1202 struct omap_tipb_bridge_s *s = opaque; in omap_tipb_bridge_write() local
1211 s->control = value & 0xffff; in omap_tipb_bridge_write()
1215 s->alloc = value & 0x003f; in omap_tipb_bridge_write()
1219 s->buffer = value & 0x0003; in omap_tipb_bridge_write()
1223 s->width_intr = !(value & 2); in omap_tipb_bridge_write()
1224 s->enh_control = value & 0x000f; in omap_tipb_bridge_write()
1245 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) in omap_tipb_bridge_reset() argument
1247 s->control = 0xffff; in omap_tipb_bridge_reset()
1248 s->alloc = 0x0009; in omap_tipb_bridge_reset()
1249 s->buffer = 0x0000; in omap_tipb_bridge_reset()
1250 s->enh_control = 0x000f; in omap_tipb_bridge_reset()
1257 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); in omap_tipb_bridge_init() local
1259 s->abort = abort_irq; in omap_tipb_bridge_init()
1260 omap_tipb_bridge_reset(s); in omap_tipb_bridge_init()
1262 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, in omap_tipb_bridge_init()
1263 "omap-tipb-bridge", 0x100); in omap_tipb_bridge_init()
1264 memory_region_add_subregion(memory, base, &s->iomem); in omap_tipb_bridge_init()
1266 return s; in omap_tipb_bridge_init()
1269 /* Dummy Traffic Controller's Memory Interface */
1273 struct omap_mpu_state_s *s = opaque; in omap_tcmi_read() local
1295 return s->tcmi_regs[addr >> 2]; in omap_tcmi_read()
1298 ret = s->tcmi_regs[addr >> 2]; in omap_tcmi_read()
1299 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ in omap_tcmi_read()
1311 struct omap_mpu_state_s *s = opaque; in omap_tcmi_write() local
1333 s->tcmi_regs[addr >> 2] = value; in omap_tcmi_write()
1336 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); in omap_tcmi_write()
1352 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; in omap_tcmi_reset()
1353 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; in omap_tcmi_reset()
1354 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; in omap_tcmi_reset()
1355 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; in omap_tcmi_reset()
1356 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1357 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1358 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1359 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; in omap_tcmi_reset()
1360 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; in omap_tcmi_reset()
1361 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; in omap_tcmi_reset()
1362 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; in omap_tcmi_reset()
1363 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; in omap_tcmi_reset()
1364 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; in omap_tcmi_reset()
1365 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; in omap_tcmi_reset()
1366 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; in omap_tcmi_reset()
1372 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, in omap_tcmi_init()
1373 "omap-tcmi", 0x100); in omap_tcmi_init()
1374 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); in omap_tcmi_init()
1378 /* Digital phase-locked loops control */
1388 struct dpll_ctl_s *s = opaque; in omap_dpll_read() local
1395 return s->mode; in omap_dpll_read()
1404 struct dpll_ctl_s *s = opaque; in omap_dpll_write() local
1416 diff = s->mode & value; in omap_dpll_write()
1417 s->mode = value & 0x2fff; in omap_dpll_write()
1426 omap_clk_setrate(s->dpll, div, mult); in omap_dpll_write()
1430 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); in omap_dpll_write()
1433 s->mode |= 2; in omap_dpll_write()
1445 static void omap_dpll_reset(struct dpll_ctl_s *s) in omap_dpll_reset() argument
1447 s->mode = 0x2002; in omap_dpll_reset()
1448 omap_clk_setrate(s->dpll, 1, 1); in omap_dpll_reset()
1454 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); in omap_dpll_init() local
1455 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); in omap_dpll_init()
1457 s->dpll = clk; in omap_dpll_init()
1458 omap_dpll_reset(s); in omap_dpll_init()
1460 memory_region_add_subregion(memory, base, &s->iomem); in omap_dpll_init()
1461 return s; in omap_dpll_init()
1468 struct omap_mpu_state_s *s = opaque; in omap_clkm_read() local
1476 return s->clkm.arm_ckctl; in omap_clkm_read()
1479 return s->clkm.arm_idlect1; in omap_clkm_read()
1482 return s->clkm.arm_idlect2; in omap_clkm_read()
1485 return s->clkm.arm_ewupct; in omap_clkm_read()
1488 return s->clkm.arm_rstct1; in omap_clkm_read()
1491 return s->clkm.arm_rstct2; in omap_clkm_read()
1494 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; in omap_clkm_read()
1497 return s->clkm.arm_ckout1; in omap_clkm_read()
1507 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, in omap_clkm_ckctl_update() argument
1516 clk = omap_findclk(s, "arminth_ck"); in omap_clkm_ckctl_update()
1517 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); in omap_clkm_ckctl_update()
1521 clk = omap_findclk(s, "armtim_ck"); in omap_clkm_ckctl_update()
1523 omap_clk_reparent(clk, omap_findclk(s, "clkin")); in omap_clkm_ckctl_update()
1525 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); in omap_clkm_ckctl_update()
1529 clk = omap_findclk(s, "dspmmu_ck"); in omap_clkm_ckctl_update()
1533 clk = omap_findclk(s, "tc_ck"); in omap_clkm_ckctl_update()
1537 clk = omap_findclk(s, "dsp_ck"); in omap_clkm_ckctl_update()
1541 clk = omap_findclk(s, "arm_ck"); in omap_clkm_ckctl_update()
1545 clk = omap_findclk(s, "lcd_ck"); in omap_clkm_ckctl_update()
1549 clk = omap_findclk(s, "armper_ck"); in omap_clkm_ckctl_update()
1554 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, in omap_clkm_idlect1_update() argument
1560 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); in omap_clkm_idlect1_update()
1569 clk = omap_findclk(s, clock); \ in omap_clkm_idlect1_update()
1588 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, in omap_clkm_idlect2_update() argument
1595 clk = omap_findclk(s, clock); \ in omap_clkm_idlect2_update()
1611 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, in omap_clkm_ckout1_update() argument
1617 clk = omap_findclk(s, "tclk_out"); in omap_clkm_ckout1_update()
1620 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); in omap_clkm_ckout1_update()
1624 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); in omap_clkm_ckout1_update()
1632 clk = omap_findclk(s, "dclk_out"); in omap_clkm_ckout1_update()
1635 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); in omap_clkm_ckout1_update()
1638 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); in omap_clkm_ckout1_update()
1641 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); in omap_clkm_ckout1_update()
1644 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); in omap_clkm_ckout1_update()
1649 clk = omap_findclk(s, "aclk_out"); in omap_clkm_ckout1_update()
1652 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); in omap_clkm_ckout1_update()
1656 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); in omap_clkm_ckout1_update()
1660 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); in omap_clkm_ckout1_update()
1672 struct omap_mpu_state_s *s = opaque; in omap_clkm_write() local
1687 diff = s->clkm.arm_ckctl ^ value; in omap_clkm_write()
1688 s->clkm.arm_ckctl = value & 0x7fff; in omap_clkm_write()
1689 omap_clkm_ckctl_update(s, diff, value); in omap_clkm_write()
1693 diff = s->clkm.arm_idlect1 ^ value; in omap_clkm_write()
1694 s->clkm.arm_idlect1 = value & 0x0fff; in omap_clkm_write()
1695 omap_clkm_idlect1_update(s, diff, value); in omap_clkm_write()
1699 diff = s->clkm.arm_idlect2 ^ value; in omap_clkm_write()
1700 s->clkm.arm_idlect2 = value & 0x07ff; in omap_clkm_write()
1701 omap_clkm_idlect2_update(s, diff, value); in omap_clkm_write()
1705 s->clkm.arm_ewupct = value & 0x003f; in omap_clkm_write()
1709 diff = s->clkm.arm_rstct1 ^ value; in omap_clkm_write()
1710 s->clkm.arm_rstct1 = value & 0x0007; in omap_clkm_write()
1713 s->clkm.cold_start = 0xa; in omap_clkm_write()
1716 omap_mpui_reset(s); in omap_clkm_write()
1717 omap_tipb_bridge_reset(s->private_tipb); in omap_clkm_write()
1718 omap_tipb_bridge_reset(s->public_tipb); in omap_clkm_write()
1721 clk = omap_findclk(s, "dsp_ck"); in omap_clkm_write()
1727 s->clkm.arm_rstct2 = value & 0x0001; in omap_clkm_write()
1731 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { in omap_clkm_write()
1732 s->clkm.clocking_scheme = (value >> 11) & 7; in omap_clkm_write()
1733 printf("%s: clocking scheme set to %s\n", __func__, in omap_clkm_write()
1734 clkschemename[s->clkm.clocking_scheme]); in omap_clkm_write()
1736 s->clkm.cold_start &= value & 0x3f; in omap_clkm_write()
1740 diff = s->clkm.arm_ckout1 ^ value; in omap_clkm_write()
1741 s->clkm.arm_ckout1 = value & 0x003f; in omap_clkm_write()
1742 omap_clkm_ckout1_update(s, diff, value); in omap_clkm_write()
1760 struct omap_mpu_state_s *s = opaque; in omap_clkdsp_read() local
1761 CPUState *cpu = CPU(s->cpu); in omap_clkdsp_read()
1769 return s->clkm.dsp_idlect1; in omap_clkdsp_read()
1772 return s->clkm.dsp_idlect2; in omap_clkdsp_read()
1775 return s->clkm.dsp_rstct2; in omap_clkdsp_read()
1778 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | in omap_clkdsp_read()
1779 (cpu->halted << 6); /* Quite useless... */ in omap_clkdsp_read()
1786 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, in omap_clkdsp_idlect1_update() argument
1794 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, in omap_clkdsp_idlect2_update() argument
1805 struct omap_mpu_state_s *s = opaque; in omap_clkdsp_write() local
1815 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1816 s->clkm.dsp_idlect1 = value & 0x01f7; in omap_clkdsp_write()
1817 omap_clkdsp_idlect1_update(s, diff, value); in omap_clkdsp_write()
1821 s->clkm.dsp_idlect2 = value & 0x0037; in omap_clkdsp_write()
1822 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1823 omap_clkdsp_idlect2_update(s, diff, value); in omap_clkdsp_write()
1827 s->clkm.dsp_rstct2 = value & 0x0001; in omap_clkdsp_write()
1831 s->clkm.cold_start &= value & 0x3f; in omap_clkdsp_write()
1845 static void omap_clkm_reset(struct omap_mpu_state_s *s) in omap_clkm_reset() argument
1847 if (s->wdt && s->wdt->reset) in omap_clkm_reset()
1848 s->clkm.cold_start = 0x6; in omap_clkm_reset()
1849 s->clkm.clocking_scheme = 0; in omap_clkm_reset()
1850 omap_clkm_ckctl_update(s, ~0, 0x3000); in omap_clkm_reset()
1851 s->clkm.arm_ckctl = 0x3000; in omap_clkm_reset()
1852 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); in omap_clkm_reset()
1853 s->clkm.arm_idlect1 = 0x0400; in omap_clkm_reset()
1854 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); in omap_clkm_reset()
1855 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_reset()
1856 s->clkm.arm_ewupct = 0x003f; in omap_clkm_reset()
1857 s->clkm.arm_rstct1 = 0x0000; in omap_clkm_reset()
1858 s->clkm.arm_rstct2 = 0x0000; in omap_clkm_reset()
1859 s->clkm.arm_ckout1 = 0x0015; in omap_clkm_reset()
1860 s->clkm.dpll1_mode = 0x2002; in omap_clkm_reset()
1861 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); in omap_clkm_reset()
1862 s->clkm.dsp_idlect1 = 0x0040; in omap_clkm_reset()
1863 omap_clkdsp_idlect2_update(s, ~0, 0x0000); in omap_clkm_reset()
1864 s->clkm.dsp_idlect2 = 0x0000; in omap_clkm_reset()
1865 s->clkm.dsp_rstct2 = 0x0000; in omap_clkm_reset()
1869 hwaddr dsp_base, struct omap_mpu_state_s *s) in omap_clkm_init() argument
1871 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, in omap_clkm_init()
1872 "omap-clkm", 0x100); in omap_clkm_init()
1873 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, in omap_clkm_init()
1874 "omap-clkdsp", 0x1000); in omap_clkm_init()
1876 s->clkm.arm_idlect1 = 0x03ff; in omap_clkm_init()
1877 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_init()
1878 s->clkm.dsp_idlect1 = 0x0002; in omap_clkm_init()
1879 omap_clkm_reset(s); in omap_clkm_init()
1880 s->clkm.cold_start = 0x3a; in omap_clkm_init()
1882 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); in omap_clkm_init()
1883 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); in omap_clkm_init()
1915 struct omap_mpuio_s *s = opaque; in omap_mpuio_set() local
1916 uint16_t prev = s->inputs; in omap_mpuio_set()
1919 s->inputs |= 1 << line; in omap_mpuio_set()
1921 s->inputs &= ~(1 << line); in omap_mpuio_set()
1923 if (((1 << line) & s->dir & ~s->mask) && s->clk) { in omap_mpuio_set()
1924 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { in omap_mpuio_set()
1925 s->ints |= 1 << line; in omap_mpuio_set()
1926 qemu_irq_raise(s->irq); in omap_mpuio_set()
1929 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ in omap_mpuio_set()
1930 (s->event >> 1) == line) /* PIN_SELECT */ in omap_mpuio_set()
1931 s->latch = s->inputs; in omap_mpuio_set()
1935 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) in omap_mpuio_kbd_update() argument
1938 uint8_t *row, rows = 0, cols = ~s->cols; in omap_mpuio_kbd_update()
1940 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) in omap_mpuio_kbd_update()
1944 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); in omap_mpuio_kbd_update()
1945 s->row_latch = ~rows; in omap_mpuio_kbd_update()
1951 struct omap_mpuio_s *s = opaque; in omap_mpuio_read() local
1961 return s->inputs; in omap_mpuio_read()
1964 return s->outputs; in omap_mpuio_read()
1967 return s->dir; in omap_mpuio_read()
1970 return s->row_latch; in omap_mpuio_read()
1973 return s->cols; in omap_mpuio_read()
1976 return s->event; in omap_mpuio_read()
1979 return s->edge; in omap_mpuio_read()
1982 return (~s->row_latch & 0x1f) && !s->kbd_mask; in omap_mpuio_read()
1985 ret = s->ints; in omap_mpuio_read()
1986 s->ints &= s->mask; in omap_mpuio_read()
1988 qemu_irq_lower(s->irq); in omap_mpuio_read()
1992 return s->kbd_mask; in omap_mpuio_read()
1995 return s->mask; in omap_mpuio_read()
1998 return s->debounce; in omap_mpuio_read()
2001 return s->latch; in omap_mpuio_read()
2011 struct omap_mpuio_s *s = opaque; in omap_mpuio_write() local
2023 diff = (s->outputs ^ value) & ~s->dir; in omap_mpuio_write()
2024 s->outputs = value; in omap_mpuio_write()
2026 if (s->handler[ln]) in omap_mpuio_write()
2027 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2033 diff = s->outputs & (s->dir ^ value); in omap_mpuio_write()
2034 s->dir = value; in omap_mpuio_write()
2036 value = s->outputs & ~s->dir; in omap_mpuio_write()
2038 if (s->handler[ln]) in omap_mpuio_write()
2039 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2045 s->cols = value; in omap_mpuio_write()
2046 omap_mpuio_kbd_update(s); in omap_mpuio_write()
2050 s->event = value & 0x1f; in omap_mpuio_write()
2054 s->edge = value; in omap_mpuio_write()
2058 s->kbd_mask = value & 1; in omap_mpuio_write()
2059 omap_mpuio_kbd_update(s); in omap_mpuio_write()
2063 s->mask = value; in omap_mpuio_write()
2067 s->debounce = value & 0x1ff; in omap_mpuio_write()
2090 static void omap_mpuio_reset(struct omap_mpuio_s *s) in omap_mpuio_reset() argument
2092 s->inputs = 0; in omap_mpuio_reset()
2093 s->outputs = 0; in omap_mpuio_reset()
2094 s->dir = ~0; in omap_mpuio_reset()
2095 s->event = 0; in omap_mpuio_reset()
2096 s->edge = 0; in omap_mpuio_reset()
2097 s->kbd_mask = 0; in omap_mpuio_reset()
2098 s->mask = 0; in omap_mpuio_reset()
2099 s->debounce = 0; in omap_mpuio_reset()
2100 s->latch = 0; in omap_mpuio_reset()
2101 s->ints = 0; in omap_mpuio_reset()
2102 s->row_latch = 0x1f; in omap_mpuio_reset()
2103 s->clk = 1; in omap_mpuio_reset()
2108 struct omap_mpuio_s *s = opaque; in omap_mpuio_onoff() local
2110 s->clk = on; in omap_mpuio_onoff()
2112 omap_mpuio_kbd_update(s); in omap_mpuio_onoff()
2120 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); in omap_mpuio_init() local
2122 s->irq = gpio_int; in omap_mpuio_init()
2123 s->kbd_irq = kbd_int; in omap_mpuio_init()
2124 s->wakeup = wakeup; in omap_mpuio_init()
2125 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); in omap_mpuio_init()
2126 omap_mpuio_reset(s); in omap_mpuio_init()
2128 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, in omap_mpuio_init()
2129 "omap-mpuio", 0x800); in omap_mpuio_init()
2130 memory_region_add_subregion(memory, base, &s->iomem); in omap_mpuio_init()
2132 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); in omap_mpuio_init()
2134 return s; in omap_mpuio_init()
2137 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) in omap_mpuio_in_get() argument
2139 return s->in; in omap_mpuio_in_get()
2142 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) in omap_mpuio_out_set() argument
2145 hw_error("%s: No GPIO line %i\n", __func__, line); in omap_mpuio_out_set()
2146 s->handler[line] = handler; in omap_mpuio_out_set()
2149 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) in omap_mpuio_key() argument
2152 hw_error("%s: No key %i-%i\n", __func__, col, row); in omap_mpuio_key()
2155 s->buttons[row] |= 1 << col; in omap_mpuio_key()
2157 s->buttons[row] &= ~(1 << col); in omap_mpuio_key()
2159 omap_mpuio_kbd_update(s); in omap_mpuio_key()
2175 static void omap_uwire_transfer_start(struct omap_uwire_s *s) in omap_uwire_transfer_start() argument
2177 int chipselect = (s->control >> 10) & 3; /* INDEX */ in omap_uwire_transfer_start()
2179 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ in omap_uwire_transfer_start()
2180 if (s->control & (1 << 12)) { /* CS_CMD */ in omap_uwire_transfer_start()
2183 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); in omap_uwire_transfer_start()
2185 s->control &= ~(1 << 14); /* CSRB */ in omap_uwire_transfer_start()
2186 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2190 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ in omap_uwire_transfer_start()
2191 if (s->control & (1 << 12)) { /* CS_CMD */ in omap_uwire_transfer_start()
2194 s->control |= 1 << 15; /* RDRB */ in omap_uwire_transfer_start()
2195 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2202 struct omap_uwire_s *s = opaque; in omap_uwire_read() local
2211 s->control &= ~(1 << 15); /* RDRB */ in omap_uwire_read()
2212 return s->rxbuf; in omap_uwire_read()
2215 return s->control; in omap_uwire_read()
2218 return s->setup[0]; in omap_uwire_read()
2220 return s->setup[1]; in omap_uwire_read()
2222 return s->setup[2]; in omap_uwire_read()
2224 return s->setup[3]; in omap_uwire_read()
2226 return s->setup[4]; in omap_uwire_read()
2236 struct omap_uwire_s *s = opaque; in omap_uwire_write() local
2246 s->txbuf = value; /* TD */ in omap_uwire_write()
2247 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ in omap_uwire_write()
2248 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ in omap_uwire_write()
2249 (s->control & (1 << 12)))) { /* CS_CMD */ in omap_uwire_write()
2250 s->control |= 1 << 14; /* CSRB */ in omap_uwire_write()
2251 omap_uwire_transfer_start(s); in omap_uwire_write()
2256 s->control = value & 0x1fff; in omap_uwire_write()
2258 omap_uwire_transfer_start(s); in omap_uwire_write()
2262 s->setup[0] = value & 0x003f; in omap_uwire_write()
2266 s->setup[1] = value & 0x0fc0; in omap_uwire_write()
2270 s->setup[2] = value & 0x0003; in omap_uwire_write()
2274 s->setup[3] = value & 0x0001; in omap_uwire_write()
2278 s->setup[4] = value & 0x000f; in omap_uwire_write()
2293 static void omap_uwire_reset(struct omap_uwire_s *s) in omap_uwire_reset() argument
2295 s->control = 0; in omap_uwire_reset()
2296 s->setup[0] = 0; in omap_uwire_reset()
2297 s->setup[1] = 0; in omap_uwire_reset()
2298 s->setup[2] = 0; in omap_uwire_reset()
2299 s->setup[3] = 0; in omap_uwire_reset()
2300 s->setup[4] = 0; in omap_uwire_reset()
2309 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); in omap_uwire_init() local
2311 s->txirq = txirq; in omap_uwire_init()
2312 s->rxirq = rxirq; in omap_uwire_init()
2313 s->txdrq = dma; in omap_uwire_init()
2314 omap_uwire_reset(s); in omap_uwire_init()
2316 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); in omap_uwire_init()
2317 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_uwire_init()
2319 return s; in omap_uwire_init()
2322 /* Pseudonoise Pulse-Width Light Modulator */
2331 static void omap_pwl_update(struct omap_pwl_s *s) in omap_pwl_update() argument
2333 int output = (s->clk && s->enable) ? s->level : 0; in omap_pwl_update()
2335 if (output != s->output) { in omap_pwl_update()
2336 s->output = output; in omap_pwl_update()
2337 printf("%s: Backlight now at %i/256\n", __func__, output); in omap_pwl_update()
2343 struct omap_pwl_s *s = opaque; in omap_pwl_read() local
2352 return s->level; in omap_pwl_read()
2354 return s->enable; in omap_pwl_read()
2363 struct omap_pwl_s *s = opaque; in omap_pwl_write() local
2373 s->level = value; in omap_pwl_write()
2374 omap_pwl_update(s); in omap_pwl_write()
2377 s->enable = value & 1; in omap_pwl_write()
2378 omap_pwl_update(s); in omap_pwl_write()
2392 static void omap_pwl_reset(struct omap_pwl_s *s) in omap_pwl_reset() argument
2394 s->output = 0; in omap_pwl_reset()
2395 s->level = 0; in omap_pwl_reset()
2396 s->enable = 0; in omap_pwl_reset()
2397 s->clk = 1; in omap_pwl_reset()
2398 omap_pwl_update(s); in omap_pwl_reset()
2403 struct omap_pwl_s *s = opaque; in omap_pwl_clk_update() local
2405 s->clk = on; in omap_pwl_clk_update()
2406 omap_pwl_update(s); in omap_pwl_clk_update()
2413 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); in omap_pwl_init() local
2415 omap_pwl_reset(s); in omap_pwl_init()
2417 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, in omap_pwl_init()
2418 "omap-pwl", 0x800); in omap_pwl_init()
2419 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_pwl_init()
2421 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); in omap_pwl_init()
2422 return s; in omap_pwl_init()
2425 /* Pulse-Width Tone module */
2436 struct omap_pwt_s *s = opaque; in omap_pwt_read() local
2445 return s->frc; in omap_pwt_read()
2447 return s->vrc; in omap_pwt_read()
2449 return s->gcr; in omap_pwt_read()
2458 struct omap_pwt_s *s = opaque; in omap_pwt_write() local
2468 s->frc = value & 0x3f; in omap_pwt_write()
2471 if ((value ^ s->vrc) & 1) { in omap_pwt_write()
2473 printf("%s: %iHz buzz on\n", __func__, (int) in omap_pwt_write()
2474 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ in omap_pwt_write()
2475 ((omap_clk_getrate(s->clk) >> 3) / in omap_pwt_write()
2476 /* Pre-multiplexer divider */ in omap_pwt_write()
2477 ((s->gcr & 2) ? 1 : 154) / in omap_pwt_write()
2490 printf("%s: silence!\n", __func__); in omap_pwt_write()
2492 s->vrc = value & 0x7f; in omap_pwt_write()
2495 s->gcr = value & 3; in omap_pwt_write()
2509 static void omap_pwt_reset(struct omap_pwt_s *s) in omap_pwt_reset() argument
2511 s->frc = 0; in omap_pwt_reset()
2512 s->vrc = 0; in omap_pwt_reset()
2513 s->gcr = 0; in omap_pwt_reset()
2520 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); in omap_pwt_init() local
2521 s->clk = clk; in omap_pwt_init()
2522 omap_pwt_reset(s); in omap_pwt_init()
2524 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, in omap_pwt_init()
2525 "omap-pwt", 0x800); in omap_pwt_init()
2526 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_pwt_init()
2527 return s; in omap_pwt_init()
2530 /* Real-time Clock module */
2552 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) in omap_rtc_interrupts_update() argument
2554 /* s->alarm is level-triggered */ in omap_rtc_interrupts_update()
2555 qemu_set_irq(s->alarm, (s->status >> 6) & 1); in omap_rtc_interrupts_update()
2558 static void omap_rtc_alarm_update(struct omap_rtc_s *s) in omap_rtc_alarm_update() argument
2560 s->alarm_ti = mktimegm(&s->alarm_tm); in omap_rtc_alarm_update()
2561 if (s->alarm_ti == -1) in omap_rtc_alarm_update()
2562 printf("%s: conversion failed\n", __func__); in omap_rtc_alarm_update()
2567 struct omap_rtc_s *s = opaque; in omap_rtc_read() local
2577 return to_bcd(s->current_tm.tm_sec); in omap_rtc_read()
2580 return to_bcd(s->current_tm.tm_min); in omap_rtc_read()
2583 if (s->pm_am) in omap_rtc_read()
2584 return ((s->current_tm.tm_hour > 11) << 7) | in omap_rtc_read()
2585 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); in omap_rtc_read()
2587 return to_bcd(s->current_tm.tm_hour); in omap_rtc_read()
2590 return to_bcd(s->current_tm.tm_mday); in omap_rtc_read()
2593 return to_bcd(s->current_tm.tm_mon + 1); in omap_rtc_read()
2596 return to_bcd(s->current_tm.tm_year % 100); in omap_rtc_read()
2599 return s->current_tm.tm_wday; in omap_rtc_read()
2602 return to_bcd(s->alarm_tm.tm_sec); in omap_rtc_read()
2605 return to_bcd(s->alarm_tm.tm_min); in omap_rtc_read()
2608 if (s->pm_am) in omap_rtc_read()
2609 return ((s->alarm_tm.tm_hour > 11) << 7) | in omap_rtc_read()
2610 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); in omap_rtc_read()
2612 return to_bcd(s->alarm_tm.tm_hour); in omap_rtc_read()
2615 return to_bcd(s->alarm_tm.tm_mday); in omap_rtc_read()
2618 return to_bcd(s->alarm_tm.tm_mon + 1); in omap_rtc_read()
2621 return to_bcd(s->alarm_tm.tm_year % 100); in omap_rtc_read()
2624 return (s->pm_am << 3) | (s->auto_comp << 2) | in omap_rtc_read()
2625 (s->round << 1) | s->running; in omap_rtc_read()
2628 i = s->status; in omap_rtc_read()
2629 s->status &= ~0x3d; in omap_rtc_read()
2633 return s->interrupts; in omap_rtc_read()
2636 return ((uint16_t) s->comp_reg) & 0xff; in omap_rtc_read()
2639 return ((uint16_t) s->comp_reg) >> 8; in omap_rtc_read()
2649 struct omap_rtc_s *s = opaque; in omap_rtc_write() local
2662 printf("RTC SEC_REG <-- %02x\n", value); in omap_rtc_write()
2664 s->ti -= s->current_tm.tm_sec; in omap_rtc_write()
2665 s->ti += from_bcd(value); in omap_rtc_write()
2670 printf("RTC MIN_REG <-- %02x\n", value); in omap_rtc_write()
2672 s->ti -= s->current_tm.tm_min * 60; in omap_rtc_write()
2673 s->ti += from_bcd(value) * 60; in omap_rtc_write()
2678 printf("RTC HRS_REG <-- %02x\n", value); in omap_rtc_write()
2680 s->ti -= s->current_tm.tm_hour * 3600; in omap_rtc_write()
2681 if (s->pm_am) { in omap_rtc_write()
2682 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; in omap_rtc_write()
2683 s->ti += ((value >> 7) & 1) * 43200; in omap_rtc_write()
2685 s->ti += from_bcd(value & 0x3f) * 3600; in omap_rtc_write()
2690 printf("RTC DAY_REG <-- %02x\n", value); in omap_rtc_write()
2692 s->ti -= s->current_tm.tm_mday * 86400; in omap_rtc_write()
2693 s->ti += from_bcd(value) * 86400; in omap_rtc_write()
2698 printf("RTC MTH_REG <-- %02x\n", value); in omap_rtc_write()
2700 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); in omap_rtc_write()
2702 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2705 if (ti[0] != -1 && ti[1] != -1) { in omap_rtc_write()
2706 s->ti -= ti[0]; in omap_rtc_write()
2707 s->ti += ti[1]; in omap_rtc_write()
2710 s->ti -= s->current_tm.tm_mon * 2592000; in omap_rtc_write()
2711 s->ti += from_bcd(value) * 2592000; in omap_rtc_write()
2717 printf("RTC YRS_REG <-- %02x\n", value); in omap_rtc_write()
2719 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); in omap_rtc_write()
2720 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); in omap_rtc_write()
2721 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2724 if (ti[0] != -1 && ti[1] != -1) { in omap_rtc_write()
2725 s->ti -= ti[0]; in omap_rtc_write()
2726 s->ti += ti[1]; in omap_rtc_write()
2729 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; in omap_rtc_write()
2730 s->ti += (time_t)from_bcd(value) * 31536000; in omap_rtc_write()
2739 printf("ALM SEC_REG <-- %02x\n", value); in omap_rtc_write()
2741 s->alarm_tm.tm_sec = from_bcd(value); in omap_rtc_write()
2742 omap_rtc_alarm_update(s); in omap_rtc_write()
2747 printf("ALM MIN_REG <-- %02x\n", value); in omap_rtc_write()
2749 s->alarm_tm.tm_min = from_bcd(value); in omap_rtc_write()
2750 omap_rtc_alarm_update(s); in omap_rtc_write()
2755 printf("ALM HRS_REG <-- %02x\n", value); in omap_rtc_write()
2757 if (s->pm_am) in omap_rtc_write()
2758 s->alarm_tm.tm_hour = in omap_rtc_write()
2762 s->alarm_tm.tm_hour = from_bcd(value); in omap_rtc_write()
2763 omap_rtc_alarm_update(s); in omap_rtc_write()
2768 printf("ALM DAY_REG <-- %02x\n", value); in omap_rtc_write()
2770 s->alarm_tm.tm_mday = from_bcd(value); in omap_rtc_write()
2771 omap_rtc_alarm_update(s); in omap_rtc_write()
2776 printf("ALM MON_REG <-- %02x\n", value); in omap_rtc_write()
2778 s->alarm_tm.tm_mon = from_bcd(value); in omap_rtc_write()
2779 omap_rtc_alarm_update(s); in omap_rtc_write()
2784 printf("ALM YRS_REG <-- %02x\n", value); in omap_rtc_write()
2786 s->alarm_tm.tm_year = from_bcd(value); in omap_rtc_write()
2787 omap_rtc_alarm_update(s); in omap_rtc_write()
2792 printf("RTC CONTROL <-- %02x\n", value); in omap_rtc_write()
2794 s->pm_am = (value >> 3) & 1; in omap_rtc_write()
2795 s->auto_comp = (value >> 2) & 1; in omap_rtc_write()
2796 s->round = (value >> 1) & 1; in omap_rtc_write()
2797 s->running = value & 1; in omap_rtc_write()
2798 s->status &= 0xfd; in omap_rtc_write()
2799 s->status |= s->running << 1; in omap_rtc_write()
2804 printf("RTC STATUSL <-- %02x\n", value); in omap_rtc_write()
2806 s->status &= ~((value & 0xc0) ^ 0x80); in omap_rtc_write()
2807 omap_rtc_interrupts_update(s); in omap_rtc_write()
2812 printf("RTC INTRS <-- %02x\n", value); in omap_rtc_write()
2814 s->interrupts = value; in omap_rtc_write()
2819 printf("RTC COMPLSB <-- %02x\n", value); in omap_rtc_write()
2821 s->comp_reg &= 0xff00; in omap_rtc_write()
2822 s->comp_reg |= 0x00ff & value; in omap_rtc_write()
2827 printf("RTC COMPMSB <-- %02x\n", value); in omap_rtc_write()
2829 s->comp_reg &= 0x00ff; in omap_rtc_write()
2830 s->comp_reg |= 0xff00 & (value << 8); in omap_rtc_write()
2847 struct omap_rtc_s *s = opaque; in omap_rtc_tick() local
2849 if (s->round) { in omap_rtc_tick()
2851 if (s->current_tm.tm_sec < 30) in omap_rtc_tick()
2852 s->ti -= s->current_tm.tm_sec; in omap_rtc_tick()
2854 s->ti += 60 - s->current_tm.tm_sec; in omap_rtc_tick()
2856 s->round = 0; in omap_rtc_tick()
2859 localtime_r(&s->ti, &s->current_tm); in omap_rtc_tick()
2861 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { in omap_rtc_tick()
2862 s->status |= 0x40; in omap_rtc_tick()
2863 omap_rtc_interrupts_update(s); in omap_rtc_tick()
2866 if (s->interrupts & 0x04) in omap_rtc_tick()
2867 switch (s->interrupts & 3) { in omap_rtc_tick()
2869 s->status |= 0x04; in omap_rtc_tick()
2870 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2873 if (s->current_tm.tm_sec) in omap_rtc_tick()
2875 s->status |= 0x08; in omap_rtc_tick()
2876 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2879 if (s->current_tm.tm_sec || s->current_tm.tm_min) in omap_rtc_tick()
2881 s->status |= 0x10; in omap_rtc_tick()
2882 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2885 if (s->current_tm.tm_sec || in omap_rtc_tick()
2886 s->current_tm.tm_min || s->current_tm.tm_hour) in omap_rtc_tick()
2888 s->status |= 0x20; in omap_rtc_tick()
2889 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2894 if (s->running) in omap_rtc_tick()
2895 s->ti ++; in omap_rtc_tick()
2896 s->tick += 1000; in omap_rtc_tick()
2902 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) in omap_rtc_tick()
2903 s->tick += s->comp_reg * 1000 / 32768; in omap_rtc_tick()
2905 timer_mod(s->clk, s->tick); in omap_rtc_tick()
2908 static void omap_rtc_reset(struct omap_rtc_s *s) in omap_rtc_reset() argument
2912 s->interrupts = 0; in omap_rtc_reset()
2913 s->comp_reg = 0; in omap_rtc_reset()
2914 s->running = 0; in omap_rtc_reset()
2915 s->pm_am = 0; in omap_rtc_reset()
2916 s->auto_comp = 0; in omap_rtc_reset()
2917 s->round = 0; in omap_rtc_reset()
2918 s->tick = qemu_clock_get_ms(rtc_clock); in omap_rtc_reset()
2919 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); in omap_rtc_reset()
2920 s->alarm_tm.tm_mday = 0x01; in omap_rtc_reset()
2921 s->status = 1 << 7; in omap_rtc_reset()
2923 s->ti = mktimegm(&tm); in omap_rtc_reset()
2925 omap_rtc_alarm_update(s); in omap_rtc_reset()
2926 omap_rtc_tick(s); in omap_rtc_reset()
2934 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); in omap_rtc_init() local
2936 s->irq = timerirq; in omap_rtc_init()
2937 s->alarm = alarmirq; in omap_rtc_init()
2938 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); in omap_rtc_init()
2940 omap_rtc_reset(s); in omap_rtc_init()
2942 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, in omap_rtc_init()
2943 "omap-rtc", 0x800); in omap_rtc_init()
2944 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_rtc_init()
2946 return s; in omap_rtc_init()
2949 /* Multi-channel Buffered Serial Port interfaces */
2975 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) in omap_mcbsp_intr_update() argument
2979 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ in omap_mcbsp_intr_update()
2981 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ in omap_mcbsp_intr_update()
2984 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ in omap_mcbsp_intr_update()
2992 qemu_irq_pulse(s->rxirq); in omap_mcbsp_intr_update()
2994 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ in omap_mcbsp_intr_update()
2996 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ in omap_mcbsp_intr_update()
2999 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ in omap_mcbsp_intr_update()
3007 qemu_irq_pulse(s->txirq); in omap_mcbsp_intr_update()
3010 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) in omap_mcbsp_rx_newdata() argument
3012 if ((s->spcr[0] >> 1) & 1) /* RRDY */ in omap_mcbsp_rx_newdata()
3013 s->spcr[0] |= 1 << 2; /* RFULL */ in omap_mcbsp_rx_newdata()
3014 s->spcr[0] |= 1 << 1; /* RRDY */ in omap_mcbsp_rx_newdata()
3015 qemu_irq_raise(s->rxdrq); in omap_mcbsp_rx_newdata()
3016 omap_mcbsp_intr_update(s); in omap_mcbsp_rx_newdata()
3021 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_source_tick() local
3022 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; in omap_mcbsp_source_tick()
3024 if (!s->rx_rate) in omap_mcbsp_source_tick()
3026 if (s->rx_req) in omap_mcbsp_source_tick()
3027 printf("%s: Rx FIFO overrun\n", __func__); in omap_mcbsp_source_tick()
3029 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; in omap_mcbsp_source_tick()
3031 omap_mcbsp_rx_newdata(s); in omap_mcbsp_source_tick()
3032 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in omap_mcbsp_source_tick()
3036 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) in omap_mcbsp_rx_start() argument
3038 if (!s->codec || !s->codec->rts) in omap_mcbsp_rx_start()
3039 omap_mcbsp_source_tick(s); in omap_mcbsp_rx_start()
3040 else if (s->codec->in.len) { in omap_mcbsp_rx_start()
3041 s->rx_req = s->codec->in.len; in omap_mcbsp_rx_start()
3042 omap_mcbsp_rx_newdata(s); in omap_mcbsp_rx_start()
3046 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) in omap_mcbsp_rx_stop() argument
3048 timer_del(s->source_timer); in omap_mcbsp_rx_stop()
3051 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) in omap_mcbsp_rx_done() argument
3053 s->spcr[0] &= ~(1 << 1); /* RRDY */ in omap_mcbsp_rx_done()
3054 qemu_irq_lower(s->rxdrq); in omap_mcbsp_rx_done()
3055 omap_mcbsp_intr_update(s); in omap_mcbsp_rx_done()
3058 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) in omap_mcbsp_tx_newdata() argument
3060 s->spcr[1] |= 1 << 1; /* XRDY */ in omap_mcbsp_tx_newdata()
3061 qemu_irq_raise(s->txdrq); in omap_mcbsp_tx_newdata()
3062 omap_mcbsp_intr_update(s); in omap_mcbsp_tx_newdata()
3067 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_sink_tick() local
3068 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; in omap_mcbsp_sink_tick()
3070 if (!s->tx_rate) in omap_mcbsp_sink_tick()
3072 if (s->tx_req) in omap_mcbsp_sink_tick()
3073 printf("%s: Tx FIFO underrun\n", __func__); in omap_mcbsp_sink_tick()
3075 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; in omap_mcbsp_sink_tick()
3077 omap_mcbsp_tx_newdata(s); in omap_mcbsp_sink_tick()
3078 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in omap_mcbsp_sink_tick()
3082 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) in omap_mcbsp_tx_start() argument
3084 if (!s->codec || !s->codec->cts) in omap_mcbsp_tx_start()
3085 omap_mcbsp_sink_tick(s); in omap_mcbsp_tx_start()
3086 else if (s->codec->out.size) { in omap_mcbsp_tx_start()
3087 s->tx_req = s->codec->out.size; in omap_mcbsp_tx_start()
3088 omap_mcbsp_tx_newdata(s); in omap_mcbsp_tx_start()
3092 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) in omap_mcbsp_tx_done() argument
3094 s->spcr[1] &= ~(1 << 1); /* XRDY */ in omap_mcbsp_tx_done()
3095 qemu_irq_lower(s->txdrq); in omap_mcbsp_tx_done()
3096 omap_mcbsp_intr_update(s); in omap_mcbsp_tx_done()
3097 if (s->codec && s->codec->cts) in omap_mcbsp_tx_done()
3098 s->codec->tx_swallow(s->codec->opaque); in omap_mcbsp_tx_done()
3101 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) in omap_mcbsp_tx_stop() argument
3103 s->tx_req = 0; in omap_mcbsp_tx_stop()
3104 omap_mcbsp_tx_done(s); in omap_mcbsp_tx_stop()
3105 timer_del(s->sink_timer); in omap_mcbsp_tx_stop()
3108 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) in omap_mcbsp_req_update() argument
3115 if (s->spcr[1] & (1 << 6)) { /* GRST */ in omap_mcbsp_req_update()
3116 if (s->spcr[0] & (1 << 0)) { /* RRST */ in omap_mcbsp_req_update()
3117 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ in omap_mcbsp_req_update()
3118 (s->pcr & (1 << 8))) { /* CLKRM */ in omap_mcbsp_req_update()
3119 if (~s->pcr & (1 << 7)) /* SCLKME */ in omap_mcbsp_req_update()
3121 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3123 if (s->codec) in omap_mcbsp_req_update()
3124 rx_rate = s->codec->rx_rate; in omap_mcbsp_req_update()
3127 if (s->spcr[1] & (1 << 0)) { /* XRST */ in omap_mcbsp_req_update()
3128 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ in omap_mcbsp_req_update()
3129 (s->pcr & (1 << 9))) { /* CLKXM */ in omap_mcbsp_req_update()
3130 if (~s->pcr & (1 << 7)) /* SCLKME */ in omap_mcbsp_req_update()
3132 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3134 if (s->codec) in omap_mcbsp_req_update()
3135 tx_rate = s->codec->tx_rate; in omap_mcbsp_req_update()
3138 prev_tx_rate = s->tx_rate; in omap_mcbsp_req_update()
3139 prev_rx_rate = s->rx_rate; in omap_mcbsp_req_update()
3140 s->tx_rate = tx_rate; in omap_mcbsp_req_update()
3141 s->rx_rate = rx_rate; in omap_mcbsp_req_update()
3143 if (s->codec) in omap_mcbsp_req_update()
3144 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); in omap_mcbsp_req_update()
3147 omap_mcbsp_tx_start(s); in omap_mcbsp_req_update()
3148 else if (s->tx_rate && !tx_rate) in omap_mcbsp_req_update()
3149 omap_mcbsp_tx_stop(s); in omap_mcbsp_req_update()
3152 omap_mcbsp_rx_start(s); in omap_mcbsp_req_update()
3154 omap_mcbsp_rx_stop(s); in omap_mcbsp_req_update()
3160 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_read() local
3170 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ in omap_mcbsp_read()
3174 if (s->rx_req < 2) { in omap_mcbsp_read()
3175 printf("%s: Rx FIFO underrun\n", __func__); in omap_mcbsp_read()
3176 omap_mcbsp_rx_done(s); in omap_mcbsp_read()
3178 s->tx_req -= 2; in omap_mcbsp_read()
3179 if (s->codec && s->codec->in.len >= 2) { in omap_mcbsp_read()
3180 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; in omap_mcbsp_read()
3181 ret |= s->codec->in.fifo[s->codec->in.start ++]; in omap_mcbsp_read()
3182 s->codec->in.len -= 2; in omap_mcbsp_read()
3185 if (!s->tx_req) in omap_mcbsp_read()
3186 omap_mcbsp_rx_done(s); in omap_mcbsp_read()
3196 return s->spcr[1]; in omap_mcbsp_read()
3198 return s->spcr[0]; in omap_mcbsp_read()
3200 return s->rcr[1]; in omap_mcbsp_read()
3202 return s->rcr[0]; in omap_mcbsp_read()
3204 return s->xcr[1]; in omap_mcbsp_read()
3206 return s->xcr[0]; in omap_mcbsp_read()
3208 return s->srgr[1]; in omap_mcbsp_read()
3210 return s->srgr[0]; in omap_mcbsp_read()
3212 return s->mcr[1]; in omap_mcbsp_read()
3214 return s->mcr[0]; in omap_mcbsp_read()
3216 return s->rcer[0]; in omap_mcbsp_read()
3218 return s->rcer[1]; in omap_mcbsp_read()
3220 return s->xcer[0]; in omap_mcbsp_read()
3222 return s->xcer[1]; in omap_mcbsp_read()
3224 return s->pcr; in omap_mcbsp_read()
3226 return s->rcer[2]; in omap_mcbsp_read()
3228 return s->rcer[3]; in omap_mcbsp_read()
3230 return s->xcer[2]; in omap_mcbsp_read()
3232 return s->xcer[3]; in omap_mcbsp_read()
3234 return s->rcer[4]; in omap_mcbsp_read()
3236 return s->rcer[5]; in omap_mcbsp_read()
3238 return s->xcer[4]; in omap_mcbsp_read()
3240 return s->xcer[5]; in omap_mcbsp_read()
3242 return s->rcer[6]; in omap_mcbsp_read()
3244 return s->rcer[7]; in omap_mcbsp_read()
3246 return s->xcer[6]; in omap_mcbsp_read()
3248 return s->xcer[7]; in omap_mcbsp_read()
3258 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_writeh() local
3268 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writeh()
3272 if (s->tx_req > 1) { in omap_mcbsp_writeh()
3273 s->tx_req -= 2; in omap_mcbsp_writeh()
3274 if (s->codec && s->codec->cts) { in omap_mcbsp_writeh()
3275 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; in omap_mcbsp_writeh()
3276 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; in omap_mcbsp_writeh()
3278 if (s->tx_req < 2) in omap_mcbsp_writeh()
3279 omap_mcbsp_tx_done(s); in omap_mcbsp_writeh()
3281 printf("%s: Tx FIFO overrun\n", __func__); in omap_mcbsp_writeh()
3285 s->spcr[1] &= 0x0002; in omap_mcbsp_writeh()
3286 s->spcr[1] |= 0x03f9 & value; in omap_mcbsp_writeh()
3287 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ in omap_mcbsp_writeh()
3289 s->spcr[1] &= ~6; in omap_mcbsp_writeh()
3290 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3293 s->spcr[0] &= 0x0006; in omap_mcbsp_writeh()
3294 s->spcr[0] |= 0xf8f9 & value; in omap_mcbsp_writeh()
3296 printf("%s: Digital Loopback mode enable attempt\n", __func__); in omap_mcbsp_writeh()
3298 s->spcr[0] &= ~6; in omap_mcbsp_writeh()
3299 s->rx_req = 0; in omap_mcbsp_writeh()
3300 omap_mcbsp_rx_done(s); in omap_mcbsp_writeh()
3302 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3306 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3309 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3312 s->xcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3315 s->xcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3318 s->srgr[1] = value & 0xffff; in omap_mcbsp_writeh()
3319 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3322 s->srgr[0] = value & 0xffff; in omap_mcbsp_writeh()
3323 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3326 s->mcr[1] = value & 0x03e3; in omap_mcbsp_writeh()
3328 printf("%s: Tx channel selection mode enable attempt\n", __func__); in omap_mcbsp_writeh()
3331 s->mcr[0] = value & 0x03e1; in omap_mcbsp_writeh()
3333 printf("%s: Rx channel selection mode enable attempt\n", __func__); in omap_mcbsp_writeh()
3336 s->rcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3339 s->rcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3342 s->xcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3345 s->xcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3348 s->pcr = value & 0x7faf; in omap_mcbsp_writeh()
3351 s->rcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3354 s->rcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3357 s->xcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3360 s->xcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3363 s->rcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3366 s->rcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3369 s->xcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3372 s->xcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3375 s->rcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3378 s->rcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3381 s->xcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3384 s->xcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3394 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_writew() local
3398 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writew()
3400 if (s->tx_req > 3) { in omap_mcbsp_writew()
3401 s->tx_req -= 4; in omap_mcbsp_writew()
3402 if (s->codec && s->codec->cts) { in omap_mcbsp_writew()
3403 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3405 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3407 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3409 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3412 if (s->tx_req < 4) in omap_mcbsp_writew()
3413 omap_mcbsp_tx_done(s); in omap_mcbsp_writew()
3415 printf("%s: Tx FIFO overrun\n", __func__); in omap_mcbsp_writew()
3443 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) in omap_mcbsp_reset() argument
3445 memset(&s->spcr, 0, sizeof(s->spcr)); in omap_mcbsp_reset()
3446 memset(&s->rcr, 0, sizeof(s->rcr)); in omap_mcbsp_reset()
3447 memset(&s->xcr, 0, sizeof(s->xcr)); in omap_mcbsp_reset()
3448 s->srgr[0] = 0x0001; in omap_mcbsp_reset()
3449 s->srgr[1] = 0x2000; in omap_mcbsp_reset()
3450 memset(&s->mcr, 0, sizeof(s->mcr)); in omap_mcbsp_reset()
3451 memset(&s->pcr, 0, sizeof(s->pcr)); in omap_mcbsp_reset()
3452 memset(&s->rcer, 0, sizeof(s->rcer)); in omap_mcbsp_reset()
3453 memset(&s->xcer, 0, sizeof(s->xcer)); in omap_mcbsp_reset()
3454 s->tx_req = 0; in omap_mcbsp_reset()
3455 s->rx_req = 0; in omap_mcbsp_reset()
3456 s->tx_rate = 0; in omap_mcbsp_reset()
3457 s->rx_rate = 0; in omap_mcbsp_reset()
3458 timer_del(s->source_timer); in omap_mcbsp_reset()
3459 timer_del(s->sink_timer); in omap_mcbsp_reset()
3467 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); in omap_mcbsp_init() local
3469 s->txirq = txirq; in omap_mcbsp_init()
3470 s->rxirq = rxirq; in omap_mcbsp_init()
3471 s->txdrq = dma[0]; in omap_mcbsp_init()
3472 s->rxdrq = dma[1]; in omap_mcbsp_init()
3473 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); in omap_mcbsp_init()
3474 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); in omap_mcbsp_init()
3475 omap_mcbsp_reset(s); in omap_mcbsp_init()
3477 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); in omap_mcbsp_init()
3478 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_mcbsp_init()
3480 return s; in omap_mcbsp_init()
3485 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_i2s_swallow() local
3487 if (s->rx_rate) { in omap_mcbsp_i2s_swallow()
3488 s->rx_req = s->codec->in.len; in omap_mcbsp_i2s_swallow()
3489 omap_mcbsp_rx_newdata(s); in omap_mcbsp_i2s_swallow()
3495 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_i2s_start() local
3497 if (s->tx_rate) { in omap_mcbsp_i2s_start()
3498 s->tx_req = s->codec->out.size; in omap_mcbsp_i2s_start()
3499 omap_mcbsp_tx_newdata(s); in omap_mcbsp_i2s_start()
3503 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) in omap_mcbsp_i2s_attach() argument
3505 s->codec = slave; in omap_mcbsp_i2s_attach()
3506 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); in omap_mcbsp_i2s_attach()
3507 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); in omap_mcbsp_i2s_attach()
3525 struct omap_lpg_s *s = opaque; in omap_lpg_tick() local
3527 if (s->cycle) in omap_lpg_tick()
3528 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); in omap_lpg_tick()
3530 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); in omap_lpg_tick()
3532 s->cycle = !s->cycle; in omap_lpg_tick()
3533 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off"); in omap_lpg_tick()
3536 static void omap_lpg_update(struct omap_lpg_s *s) in omap_lpg_update() argument
3541 if (~s->control & (1 << 6)) /* LPGRES */ in omap_lpg_update()
3543 else if (s->control & (1 << 7)) /* PERM_ON */ in omap_lpg_update()
3546 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ in omap_lpg_update()
3548 on = (s->clk && s->power) ? muldiv64(ticks, in omap_lpg_update()
3549 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ in omap_lpg_update()
3552 timer_del(s->tm); in omap_lpg_update()
3553 if (on == period && s->on < s->period) in omap_lpg_update()
3554 printf("%s: LED is on\n", __func__); in omap_lpg_update()
3555 else if (on == 0 && s->on) in omap_lpg_update()
3556 printf("%s: LED is off\n", __func__); in omap_lpg_update()
3557 else if (on && (on != s->on || period != s->period)) { in omap_lpg_update()
3558 s->cycle = 0; in omap_lpg_update()
3559 s->on = on; in omap_lpg_update()
3560 s->period = period; in omap_lpg_update()
3561 omap_lpg_tick(s); in omap_lpg_update()
3565 s->on = on; in omap_lpg_update()
3566 s->period = period; in omap_lpg_update()
3569 static void omap_lpg_reset(struct omap_lpg_s *s) in omap_lpg_reset() argument
3571 s->control = 0x00; in omap_lpg_reset()
3572 s->power = 0x00; in omap_lpg_reset()
3573 s->clk = 1; in omap_lpg_reset()
3574 omap_lpg_update(s); in omap_lpg_reset()
3579 struct omap_lpg_s *s = opaque; in omap_lpg_read() local
3588 return s->control; in omap_lpg_read()
3591 return s->power; in omap_lpg_read()
3601 struct omap_lpg_s *s = opaque; in omap_lpg_write() local
3612 omap_lpg_reset(s); in omap_lpg_write()
3613 s->control = value & 0xff; in omap_lpg_write()
3614 omap_lpg_update(s); in omap_lpg_write()
3618 s->power = value & 0x01; in omap_lpg_write()
3619 omap_lpg_update(s); in omap_lpg_write()
3636 struct omap_lpg_s *s = opaque; in omap_lpg_clk_update() local
3638 s->clk = on; in omap_lpg_clk_update()
3639 omap_lpg_update(s); in omap_lpg_clk_update()
3645 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); in omap_lpg_init() local
3647 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); in omap_lpg_init()
3649 omap_lpg_reset(s); in omap_lpg_init()
3651 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); in omap_lpg_init()
3652 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_lpg_init()
3654 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); in omap_lpg_init()
3656 return s; in omap_lpg_init()
3690 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, in omap_setup_mpui_io()
3691 "omap-mpui-io", 0x7fff); in omap_setup_mpui_io()
3693 &mpu->mpui_io_iomem); in omap_setup_mpui_io()
3701 omap_dma_reset(mpu->dma); in omap1_mpu_reset()
3702 omap_mpu_timer_reset(mpu->timer[0]); in omap1_mpu_reset()
3703 omap_mpu_timer_reset(mpu->timer[1]); in omap1_mpu_reset()
3704 omap_mpu_timer_reset(mpu->timer[2]); in omap1_mpu_reset()
3705 omap_wd_timer_reset(mpu->wdt); in omap1_mpu_reset()
3706 omap_os_timer_reset(mpu->os_timer); in omap1_mpu_reset()
3707 omap_lcdc_reset(mpu->lcd); in omap1_mpu_reset()
3711 omap_tipb_bridge_reset(mpu->private_tipb); in omap1_mpu_reset()
3712 omap_tipb_bridge_reset(mpu->public_tipb); in omap1_mpu_reset()
3713 omap_dpll_reset(mpu->dpll[0]); in omap1_mpu_reset()
3714 omap_dpll_reset(mpu->dpll[1]); in omap1_mpu_reset()
3715 omap_dpll_reset(mpu->dpll[2]); in omap1_mpu_reset()
3716 omap_uart_reset(mpu->uart[0]); in omap1_mpu_reset()
3717 omap_uart_reset(mpu->uart[1]); in omap1_mpu_reset()
3718 omap_uart_reset(mpu->uart[2]); in omap1_mpu_reset()
3719 omap_mmc_reset(mpu->mmc); in omap1_mpu_reset()
3720 omap_mpuio_reset(mpu->mpuio); in omap1_mpu_reset()
3721 omap_uwire_reset(mpu->microwire); in omap1_mpu_reset()
3722 omap_pwl_reset(mpu->pwl); in omap1_mpu_reset()
3723 omap_pwt_reset(mpu->pwt); in omap1_mpu_reset()
3724 omap_rtc_reset(mpu->rtc); in omap1_mpu_reset()
3725 omap_mcbsp_reset(mpu->mcbsp1); in omap1_mpu_reset()
3726 omap_mcbsp_reset(mpu->mcbsp2); in omap1_mpu_reset()
3727 omap_mcbsp_reset(mpu->mcbsp3); in omap1_mpu_reset()
3728 omap_lpg_reset(mpu->led[0]); in omap1_mpu_reset()
3729 omap_lpg_reset(mpu->led[1]); in omap1_mpu_reset()
3731 cpu_reset(CPU(mpu->cpu)); in omap1_mpu_reset()
3745 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3755 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3769 for (; map->phys_dsp; map ++) { in omap_setup_dsp_mapping()
3771 memory_region_init_alias(io, NULL, map->name, in omap_setup_dsp_mapping()
3772 system_memory, map->phys_mpu, map->size); in omap_setup_dsp_mapping()
3773 memory_region_add_subregion(system_memory, map->phys_dsp, io); in omap_setup_dsp_mapping()
3780 CPUState *cpu = CPU(mpu->cpu); in omap_mpu_wakeup()
3782 if (cpu->halted) { in omap_mpu_wakeup()
3807 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, in omap_validate_emiff_addr() argument
3810 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); in omap_validate_emiff_addr()
3813 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, in omap_validate_emifs_addr() argument
3816 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, in omap_validate_emifs_addr()
3820 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, in omap_validate_imif_addr() argument
3823 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); in omap_validate_imif_addr()
3826 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, in omap_validate_tipb_addr() argument
3829 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); in omap_validate_tipb_addr()
3832 static int omap_validate_local_addr(struct omap_mpu_state_s *s, in omap_validate_local_addr() argument
3838 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, in omap_validate_tipb_mpui_addr() argument
3841 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); in omap_validate_tipb_mpui_addr()
3848 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); in omap310_mpu_init() local
3855 s->mpu_model = omap310; in omap310_mpu_init()
3856 s->cpu = ARM_CPU(cpu_create(cpu_type)); in omap310_mpu_init()
3857 s->sdram_size = memory_region_size(dram); in omap310_mpu_init()
3858 s->sram_size = OMAP15XX_SRAM_SIZE; in omap310_mpu_init()
3860 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); in omap310_mpu_init()
3863 omap_clk_init(s); in omap310_mpu_init()
3865 /* Memory-mapped stuff */ in omap310_mpu_init()
3866 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, in omap310_mpu_init()
3868 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); in omap310_mpu_init()
3870 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); in omap310_mpu_init()
3872 s->ih[0] = qdev_new("omap-intc"); in omap310_mpu_init()
3873 qdev_prop_set_uint32(s->ih[0], "size", 0x100); in omap310_mpu_init()
3874 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); in omap310_mpu_init()
3875 busdev = SYS_BUS_DEVICE(s->ih[0]); in omap310_mpu_init()
3878 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); in omap310_mpu_init()
3880 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); in omap310_mpu_init()
3882 s->ih[1] = qdev_new("omap-intc"); in omap310_mpu_init()
3883 qdev_prop_set_uint32(s->ih[1], "size", 0x800); in omap310_mpu_init()
3884 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); in omap310_mpu_init()
3885 busdev = SYS_BUS_DEVICE(s->ih[1]); in omap310_mpu_init()
3888 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); in omap310_mpu_init()
3889 /* The second interrupt controller's FIQ output is not wired up */ in omap310_mpu_init()
3893 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], in omap310_mpu_init()
3896 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, in omap310_mpu_init()
3897 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), in omap310_mpu_init()
3898 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); in omap310_mpu_init()
3900 s->port[emiff ].addr_valid = omap_validate_emiff_addr; in omap310_mpu_init()
3901 s->port[emifs ].addr_valid = omap_validate_emifs_addr; in omap310_mpu_init()
3902 s->port[imif ].addr_valid = omap_validate_imif_addr; in omap310_mpu_init()
3903 s->port[tipb ].addr_valid = omap_validate_tipb_addr; in omap310_mpu_init()
3904 s->port[local ].addr_valid = omap_validate_local_addr; in omap310_mpu_init()
3905 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; in omap310_mpu_init()
3908 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram), in omap310_mpu_init()
3909 OMAP_EMIFF_BASE, s->sdram_size); in omap310_mpu_init()
3910 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), in omap310_mpu_init()
3911 OMAP_IMIF_BASE, s->sram_size); in omap310_mpu_init()
3913 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, in omap310_mpu_init()
3914 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), in omap310_mpu_init()
3915 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3916 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, in omap310_mpu_init()
3917 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), in omap310_mpu_init()
3918 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3919 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, in omap310_mpu_init()
3920 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), in omap310_mpu_init()
3921 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3923 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, in omap310_mpu_init()
3924 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), in omap310_mpu_init()
3925 omap_findclk(s, "armwdt_ck")); in omap310_mpu_init()
3927 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, in omap310_mpu_init()
3928 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), in omap310_mpu_init()
3929 omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
3931 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, in omap310_mpu_init()
3932 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), in omap310_mpu_init()
3933 omap_dma_get_lcdch(s->dma), in omap310_mpu_init()
3934 omap_findclk(s, "lcd_ck")); in omap310_mpu_init()
3936 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); in omap310_mpu_init()
3937 omap_pin_cfg_init(system_memory, 0xfffe1000, s); in omap310_mpu_init()
3938 omap_id_init(system_memory, s); in omap310_mpu_init()
3940 omap_mpui_init(system_memory, 0xfffec900, s); in omap310_mpu_init()
3942 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, in omap310_mpu_init()
3943 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), in omap310_mpu_init()
3944 omap_findclk(s, "tipb_ck")); in omap310_mpu_init()
3945 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, in omap310_mpu_init()
3946 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), in omap310_mpu_init()
3947 omap_findclk(s, "tipb_ck")); in omap310_mpu_init()
3949 omap_tcmi_init(system_memory, 0xfffecc00, s); in omap310_mpu_init()
3951 s->uart[0] = omap_uart_init(0xfffb0000, in omap310_mpu_init()
3952 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), in omap310_mpu_init()
3953 omap_findclk(s, "uart1_ck"), in omap310_mpu_init()
3954 omap_findclk(s, "uart1_ck"), in omap310_mpu_init()
3955 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], in omap310_mpu_init()
3958 s->uart[1] = omap_uart_init(0xfffb0800, in omap310_mpu_init()
3959 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), in omap310_mpu_init()
3960 omap_findclk(s, "uart2_ck"), in omap310_mpu_init()
3961 omap_findclk(s, "uart2_ck"), in omap310_mpu_init()
3962 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], in omap310_mpu_init()
3965 s->uart[2] = omap_uart_init(0xfffb9800, in omap310_mpu_init()
3966 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), in omap310_mpu_init()
3967 omap_findclk(s, "uart3_ck"), in omap310_mpu_init()
3968 omap_findclk(s, "uart3_ck"), in omap310_mpu_init()
3969 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], in omap310_mpu_init()
3973 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, in omap310_mpu_init()
3974 omap_findclk(s, "dpll1")); in omap310_mpu_init()
3975 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, in omap310_mpu_init()
3976 omap_findclk(s, "dpll2")); in omap310_mpu_init()
3977 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, in omap310_mpu_init()
3978 omap_findclk(s, "dpll3")); in omap310_mpu_init()
3984 s->mmc = omap_mmc_init(0xfffb7800, system_memory, in omap310_mpu_init()
3986 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), in omap310_mpu_init()
3987 &s->drq[OMAP_DMA_MMC_TX], in omap310_mpu_init()
3988 omap_findclk(s, "mmc_ck")); in omap310_mpu_init()
3990 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, in omap310_mpu_init()
3991 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), in omap310_mpu_init()
3992 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), in omap310_mpu_init()
3993 s->wakeup, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
3995 s->gpio = qdev_new("omap-gpio"); in omap310_mpu_init()
3996 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); in omap310_mpu_init()
3997 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); in omap310_mpu_init()
3998 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal); in omap310_mpu_init()
3999 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, in omap310_mpu_init()
4000 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); in omap310_mpu_init()
4001 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); in omap310_mpu_init()
4003 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, in omap310_mpu_init()
4004 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), in omap310_mpu_init()
4005 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), in omap310_mpu_init()
4006 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
4008 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, in omap310_mpu_init()
4009 omap_findclk(s, "armxor_ck")); in omap310_mpu_init()
4010 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, in omap310_mpu_init()
4011 omap_findclk(s, "armxor_ck")); in omap310_mpu_init()
4013 s->i2c[0] = qdev_new("omap_i2c"); in omap310_mpu_init()
4014 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); in omap310_mpu_init()
4015 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
4016 busdev = SYS_BUS_DEVICE(s->i2c[0]); in omap310_mpu_init()
4018 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); in omap310_mpu_init()
4019 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); in omap310_mpu_init()
4020 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); in omap310_mpu_init()
4023 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, in omap310_mpu_init()
4024 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), in omap310_mpu_init()
4025 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), in omap310_mpu_init()
4026 omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4028 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, in omap310_mpu_init()
4029 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), in omap310_mpu_init()
4030 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), in omap310_mpu_init()
4031 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); in omap310_mpu_init()
4032 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, in omap310_mpu_init()
4033 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4035 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4037 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
4038 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, in omap310_mpu_init()
4039 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), in omap310_mpu_init()
4040 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), in omap310_mpu_init()
4041 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); in omap310_mpu_init()
4043 s->led[0] = omap_lpg_init(system_memory, in omap310_mpu_init()
4044 0xfffbd000, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4045 s->led[1] = omap_lpg_init(system_memory, in omap310_mpu_init()
4046 0xfffbd800, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4049 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) in omap310_mpu_init()
4050 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) in omap310_mpu_init()
4051 * USB W2FC fffb4000 - fffb47ff in omap310_mpu_init()
4052 * Camera Interface fffb6800 - fffb6fff in omap310_mpu_init()
4053 * USB Host fffba000 - fffba7ff in omap310_mpu_init()
4054 * FAC fffba800 - fffbafff in omap310_mpu_init()
4055 * HDQ/1-Wire fffbc000 - fffbc7ff in omap310_mpu_init()
4056 * TIPB switches fffbc800 - fffbcfff in omap310_mpu_init()
4057 * Mailbox fffcf000 - fffcf7ff in omap310_mpu_init()
4058 * Local bus IF fffec100 - fffec1ff in omap310_mpu_init()
4059 * Local bus MMU fffec200 - fffec2ff in omap310_mpu_init()
4060 * DSP MMU fffed200 - fffed2ff in omap310_mpu_init()
4064 omap_setup_mpui_io(system_memory, s); in omap310_mpu_init()
4066 qemu_register_reset(omap1_mpu_reset, s); in omap310_mpu_init()
4068 return s; in omap310_mpu_init()