Lines Matching +full:npcm750 +full:- +full:memory +full:- +full:controller
23 #include "hw/char/serial-mm.h"
27 #include "hw/qdev-clock.h"
28 #include "hw/qdev-properties.h"
61 /* Memory blocks at the end of the address space */
78 * Interrupt lines going into the GIC. This does not include internal Cortex-A35
164 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
167 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)
187 /* Direct memory-mapped access to SPI0 CS0-1. */
193 /* Direct memory-mapped access to SPI1 CS0-3. */
201 /* Direct memory-mapped access to SPI3 CS0-3. */
228 /* Direct memory-mapped access to each SMBus Module. */
347 .board_id = -1,
353 npcm8xx_binfo.ram_size = machine->ram_size; in npcm8xx_load_kernel()
355 arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); in npcm8xx_load_kernel()
365 * NPCM750 or NPCM730). in npcm8xx_init_fuses()
367 value = cpu_to_le32(nc->disabled_modules); in npcm8xx_init_fuses()
368 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, in npcm8xx_init_fuses()
375 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); in npcm8xx_write_adc_calibration()
376 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, in npcm8xx_write_adc_calibration()
377 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); in npcm8xx_write_adc_calibration()
382 return qdev_get_gpio_in(DEVICE(&s->gic), n); in npcm8xx_irq()
390 object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, in npcm8xx_init()
393 object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu[i], in npcm8xx_init()
394 ARM_CPU_TYPE_NAME("cortex-a35")); in npcm8xx_init()
396 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in npcm8xx_init()
397 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); in npcm8xx_init()
398 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), in npcm8xx_init()
399 "power-on-straps"); in npcm8xx_init()
400 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); in npcm8xx_init()
401 object_initialize_child(obj, "otp", &s->fuse_array, in npcm8xx_init()
403 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); in npcm8xx_init()
404 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); in npcm8xx_init()
405 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); in npcm8xx_init()
407 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { in npcm8xx_init()
408 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); in npcm8xx_init()
411 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { in npcm8xx_init()
412 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); in npcm8xx_init()
416 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm8xx_init()
417 object_initialize_child(obj, "smbus[*]", &s->smbus[i], in npcm8xx_init()
419 DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i); in npcm8xx_init()
422 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { in npcm8xx_init()
423 object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_EHCI); in npcm8xx_init()
425 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { in npcm8xx_init()
426 object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI); in npcm8xx_init()
429 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); in npcm8xx_init()
430 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { in npcm8xx_init()
431 object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], in npcm8xx_init()
435 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm8xx_init()
436 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); in npcm8xx_init()
439 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { in npcm8xx_init()
440 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); in npcm8xx_init()
443 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); in npcm8xx_init()
452 if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { in npcm8xx_realize()
459 for (i = 0; i < nc->num_cpus; i++) { in npcm8xx_realize()
460 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", in npcm8xx_realize()
463 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, in npcm8xx_realize()
465 object_property_set_int(OBJECT(&s->cpu[i]), "core-count", in npcm8xx_realize()
466 nc->num_cpus, &error_abort); in npcm8xx_realize()
469 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, in npcm8xx_realize()
472 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { in npcm8xx_realize()
478 object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp); in npcm8xx_realize()
479 object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp); in npcm8xx_realize()
480 object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); in npcm8xx_realize()
481 object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true, in npcm8xx_realize()
483 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in npcm8xx_realize()
486 for (i = 0; i < nc->num_cpus; i++) { in npcm8xx_realize()
487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, in npcm8xx_realize()
488 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); in npcm8xx_realize()
489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, in npcm8xx_realize()
490 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); in npcm8xx_realize()
491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, in npcm8xx_realize()
492 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VIRQ)); in npcm8xx_realize()
493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, in npcm8xx_realize()
494 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VFIQ)); in npcm8xx_realize()
496 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, in npcm8xx_realize()
497 qdev_get_gpio_in(DEVICE(&s->gic), in npcm8xx_realize()
499 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, in npcm8xx_realize()
500 qdev_get_gpio_in(DEVICE(&s->gic), in npcm8xx_realize()
502 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, in npcm8xx_realize()
503 qdev_get_gpio_in(DEVICE(&s->gic), in npcm8xx_realize()
505 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, in npcm8xx_realize()
506 qdev_get_gpio_in(DEVICE(&s->gic), in npcm8xx_realize()
509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); in npcm8xx_realize()
510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); in npcm8xx_realize()
513 qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); in npcm8xx_realize()
514 qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); in npcm8xx_realize()
517 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", in npcm8xx_realize()
518 nc->disabled_modules, &error_abort); in npcm8xx_realize()
519 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); in npcm8xx_realize()
520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { in npcm8xx_realize()
523 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); in npcm8xx_realize()
526 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); in npcm8xx_realize()
527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); in npcm8xx_realize()
530 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); in npcm8xx_realize()
531 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); in npcm8xx_realize()
534 /* Fake Memory Controller (MC). Cannot fail. */ in npcm8xx_realize()
535 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); in npcm8xx_realize()
536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); in npcm8xx_realize()
539 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( in npcm8xx_realize()
540 DEVICE(&s->clk), "adc-clock")); in npcm8xx_realize()
541 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); in npcm8xx_realize()
542 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); in npcm8xx_realize()
543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, in npcm8xx_realize()
548 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) != ARRAY_SIZE(s->tim)); in npcm8xx_realize()
549 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { in npcm8xx_realize()
550 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); in npcm8xx_realize()
555 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( in npcm8xx_realize()
556 DEVICE(&s->clk), "timer-clock")); in npcm8xx_realize()
571 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), in npcm8xx_realize()
573 qdev_get_gpio_in_named(DEVICE(&s->clk), in npcm8xx_realize()
585 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); in npcm8xx_realize()
586 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); in npcm8xx_realize()
589 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) != ARRAY_SIZE(s->gpio)); in npcm8xx_realize()
590 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { in npcm8xx_realize()
591 Object *obj = OBJECT(&s->gpio[i]); in npcm8xx_realize()
593 object_property_set_uint(obj, "reset-pullup", in npcm8xx_realize()
595 object_property_set_uint(obj, "reset-pulldown", in npcm8xx_realize()
597 object_property_set_uint(obj, "reset-osrc", in npcm8xx_realize()
599 object_property_set_uint(obj, "reset-odsc", in npcm8xx_realize()
608 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus)); in npcm8xx_realize()
609 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm8xx_realize()
610 Object *obj = OBJECT(&s->smbus[i]); in npcm8xx_realize()
619 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) != ARRAY_SIZE(s->ehci)); in npcm8xx_realize()
620 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { in npcm8xx_realize()
621 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, in npcm8xx_realize()
623 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); in npcm8xx_realize()
624 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[i]); in npcm8xx_realize()
625 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, in npcm8xx_realize()
628 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { in npcm8xx_realize()
629 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus.0", in npcm8xx_realize()
631 object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, in npcm8xx_realize()
633 object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, in npcm8xx_realize()
635 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); in npcm8xx_realize()
636 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[i]); in npcm8xx_realize()
637 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, in npcm8xx_realize()
642 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm)); in npcm8xx_realize()
643 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm8xx_realize()
644 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); in npcm8xx_realize()
646 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( in npcm8xx_realize()
647 DEVICE(&s->clk), "apb3-clock")); in npcm8xx_realize()
654 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) != ARRAY_SIZE(s->mft)); in npcm8xx_realize()
655 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { in npcm8xx_realize()
656 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); in npcm8xx_realize()
658 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", in npcm8xx_realize()
659 qdev_get_clock_out(DEVICE(&s->clk), in npcm8xx_realize()
660 "apb4-clock")); in npcm8xx_realize()
670 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); in npcm8xx_realize()
671 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { in npcm8xx_realize()
672 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); in npcm8xx_realize()
675 object_property_set_int(OBJECT(sbd), "cs-count", in npcm8xx_realize()
677 object_property_set_int(OBJECT(sbd), "flash-size", in npcm8xx_realize()
688 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", in npcm8xx_realize()
690 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->sram); in npcm8xx_realize()
693 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", in npcm8xx_realize()
695 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->ram3); in npcm8xx_realize()
698 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, in npcm8xx_realize()
700 memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->irom); in npcm8xx_realize()
703 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); in npcm8xx_realize()
704 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); in npcm8xx_realize()
705 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, in npcm8xx_realize()
778 DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION,
787 dc->realize = npcm8xx_realize; in npcm8xx_class_init()
788 dc->user_creatable = false; in npcm8xx_class_init()
789 nc->disabled_modules = 0x00000000; in npcm8xx_class_init()
790 nc->num_cpus = NPCM8XX_MAX_NUM_CPUS; in npcm8xx_class_init()