Lines Matching +full:0 +full:xf0002000
36 #define NPCM7XX_MMIO_BA (0x80000000)
37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
40 #define NPCM7XX_OTP1_BA (0xf0189000)
41 #define NPCM7XX_OTP2_BA (0xf018a000)
44 #define NPCM7XX_L2C_BA (0xf03fc000)
45 #define NPCM7XX_CPUP_BA (0xf03fe000)
46 #define NPCM7XX_GCR_BA (0xf0800000)
47 #define NPCM7XX_CLK_BA (0xf0801000)
48 #define NPCM7XX_MC_BA (0xf0824000)
49 #define NPCM7XX_RNG_BA (0xf000b000)
52 #define NPCM7XX_EHCI_BA (0xf0806000)
53 #define NPCM7XX_OHCI_BA (0xf0807000)
56 #define NPCM7XX_ADC_BA (0xf000c000)
59 #define NPCM7XX_RAM3_BA (0xc0008000)
63 #define NPCM7XX_RAM2_BA (0xfffd0000)
65 #define NPCM7XX_ROM_BA (0xffff0000)
69 #define NPCM7XX_MMC_BA (0xf0842000)
74 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
76 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
83 NPCM7XX_ADC_IRQ = 0,
95 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
110 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
133 NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
158 0xf0008000,
159 0xf0009000,
160 0xf000a000,
165 0xf0001000,
166 0xf0002000,
167 0xf0003000,
168 0xf0004000,
173 0x80000000, /* CS0 */
174 0x88000000, /* CS1 */
179 0xa0000000, /* CS0 */
180 0xa8000000, /* CS1 */
181 0xb0000000, /* CS2 */
182 0xb8000000, /* CS3 */
187 0xf0103000,
188 0xf0104000,
193 0xf0180000,
194 0xf0181000,
195 0xf0182000,
196 0xf0183000,
197 0xf0184000,
198 0xf0185000,
199 0xf0186000,
200 0xf0187000,
205 0xf0080000,
206 0xf0081000,
207 0xf0082000,
208 0xf0083000,
209 0xf0084000,
210 0xf0085000,
211 0xf0086000,
212 0xf0087000,
213 0xf0088000,
214 0xf0089000,
215 0xf008a000,
216 0xf008b000,
217 0xf008c000,
218 0xf008d000,
219 0xf008e000,
220 0xf008f000,
225 0xf0825000,
226 0xf0826000,
231 0xf0200000,
232 0xf0201000,
237 0xf0802000,
238 0xf0804000,
250 .regs_addr = 0xf0010000,
251 .reset_pu = 0xff03ffff,
252 .reset_pd = 0x00fc0000,
254 .regs_addr = 0xf0011000,
255 .unconnected_pins = 0x0000001e,
256 .reset_pu = 0xfefffe07,
257 .reset_pd = 0x010001e0,
259 .regs_addr = 0xf0012000,
260 .reset_pu = 0x780fffff,
261 .reset_pd = 0x07f00000,
262 .reset_odsc = 0x00700000,
264 .regs_addr = 0xf0013000,
265 .reset_pu = 0x00fc0000,
266 .reset_pd = 0xff000000,
268 .regs_addr = 0xf0014000,
269 .reset_pu = 0xffffffff,
271 .regs_addr = 0xf0015000,
272 .reset_pu = 0xbf83f801,
273 .reset_pd = 0x007c0000,
274 .reset_osrc = 0x000000f1,
275 .reset_odsc = 0x3f9f80f1,
277 .regs_addr = 0xf0016000,
278 .reset_pu = 0xfc00f801,
279 .reset_pd = 0x000007fe,
280 .reset_odsc = 0x00000800,
282 .regs_addr = 0xf0017000,
283 .unconnected_pins = 0xffffff00,
284 .reset_pu = 0x0000007f,
285 .reset_osrc = 0x0000007f,
286 .reset_odsc = 0x0000007f,
298 .regs_addr = 0xfb000000,
303 .regs_addr = 0xc0000000,
313 0xe59f0010, /* ldr r0, clk_base_addr */ in npcm7xx_write_board_setup()
314 0xe59f1010, /* ldr r1, pllcon1_value */ in npcm7xx_write_board_setup()
315 0xe5801010, /* str r1, [r0, #16] */ in npcm7xx_write_board_setup()
316 0xe59f100c, /* ldr r1, clksel_value */ in npcm7xx_write_board_setup()
317 0xe5801004, /* str r1, [r0, #4] */ in npcm7xx_write_board_setup()
318 0xe12fff1e, /* bx lr */ in npcm7xx_write_board_setup()
325 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { in npcm7xx_write_board_setup()
343 0xe59f2018, /* ldr r2, bootreg_addr */ in npcm7xx_write_secondary_boot()
344 0xe3a00000, /* mov r0, #0 */ in npcm7xx_write_secondary_boot()
345 0xe5820000, /* str r0, [r2] */ in npcm7xx_write_secondary_boot()
346 0xe320f002, /* wfe */ in npcm7xx_write_secondary_boot()
347 0xe5921000, /* ldr r1, [r2] */ in npcm7xx_write_secondary_boot()
348 0xe1110001, /* tst r1, r1 */ in npcm7xx_write_secondary_boot()
349 0x0afffffb, /* beq <wfe> */ in npcm7xx_write_secondary_boot()
350 0xe12fff11, /* bx r1 */ in npcm7xx_write_secondary_boot()
355 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { in npcm7xx_write_secondary_boot()
378 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); in npcm7xx_load_kernel()
413 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { in npcm7xx_init()
431 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { in npcm7xx_init()
435 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { in npcm7xx_init()
439 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm7xx_init()
448 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { in npcm7xx_init()
453 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm7xx_init()
457 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { in npcm7xx_init()
461 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { in npcm7xx_init()
465 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { in npcm7xx_init()
469 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { in npcm7xx_init()
489 for (i = 0; i < nc->num_cpus; i++) { in npcm7xx_realize()
510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); in npcm7xx_realize()
512 for (i = 0; i < nc->num_cpus; i++) { in npcm7xx_realize()
529 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); in npcm7xx_realize()
533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); in npcm7xx_realize()
537 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); in npcm7xx_realize()
539 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); in npcm7xx_realize()
544 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); in npcm7xx_realize()
550 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); in npcm7xx_realize()
551 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, in npcm7xx_realize()
557 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { in npcm7xx_realize()
567 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); in npcm7xx_realize()
570 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { in npcm7xx_realize()
580 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, in npcm7xx_realize()
586 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { in npcm7xx_realize()
594 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); in npcm7xx_realize()
598 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { in npcm7xx_realize()
610 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr); in npcm7xx_realize()
611 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, in npcm7xx_realize()
617 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm7xx_realize()
621 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); in npcm7xx_realize()
622 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, in npcm7xx_realize()
630 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); in npcm7xx_realize()
631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, in npcm7xx_realize()
634 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", in npcm7xx_realize()
638 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); in npcm7xx_realize()
639 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, in npcm7xx_realize()
644 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm7xx_realize()
650 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); in npcm7xx_realize()
656 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { in npcm7xx_realize()
663 sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]); in npcm7xx_realize()
664 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i)); in npcm7xx_realize()
678 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { in npcm7xx_realize()
692 sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); in npcm7xx_realize()
693 int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ; in npcm7xx_realize()
694 int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ; in npcm7xx_realize()
699 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); in npcm7xx_realize()
708 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { in npcm7xx_realize()
718 sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]); in npcm7xx_realize()
719 int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ; in npcm7xx_realize()
724 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); in npcm7xx_realize()
732 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { in npcm7xx_realize()
740 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); in npcm7xx_realize()
741 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { in npcm7xx_realize()
763 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM7XX_MMC_BA); in npcm7xx_realize()
764 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, in npcm7xx_realize()
769 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { in npcm7xx_realize()
771 int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; in npcm7xx_realize()
774 sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); in npcm7xx_realize()
775 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); in npcm7xx_realize()
778 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); in npcm7xx_realize()
779 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); in npcm7xx_realize()
780 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); in npcm7xx_realize()
781 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); in npcm7xx_realize()
782 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); in npcm7xx_realize()
783 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); in npcm7xx_realize()
784 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); in npcm7xx_realize()
785 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); in npcm7xx_realize()
786 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); in npcm7xx_realize()
787 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); in npcm7xx_realize()
788 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); in npcm7xx_realize()
789 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); in npcm7xx_realize()
790 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); in npcm7xx_realize()
791 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); in npcm7xx_realize()
792 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); in npcm7xx_realize()
793 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); in npcm7xx_realize()
794 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); in npcm7xx_realize()
795 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); in npcm7xx_realize()
796 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); in npcm7xx_realize()
797 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); in npcm7xx_realize()
798 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); in npcm7xx_realize()
799 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); in npcm7xx_realize()
800 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); in npcm7xx_realize()
801 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); in npcm7xx_realize()
802 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); in npcm7xx_realize()
803 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); in npcm7xx_realize()
804 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); in npcm7xx_realize()
805 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); in npcm7xx_realize()
806 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); in npcm7xx_realize()
807 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); in npcm7xx_realize()
808 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); in npcm7xx_realize()
809 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); in npcm7xx_realize()
810 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); in npcm7xx_realize()
833 nc->disabled_modules = 0x00300395; in npcm730_class_init()
842 nc->disabled_modules = 0x00000000; in npcm750_class_init()