Lines Matching +full:0 +full:x40024000
130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
178 * 0x00000000 .. 0x0003ffff : FPGA block RAM in mps2_common_init()
179 * 0x00400000 .. 0x007fffff : ZBT SSRAM1 in mps2_common_init()
180 * 0x20000000 .. 0x2001ffff : SRAM in mps2_common_init()
181 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 in mps2_common_init()
183 * 0x60000000 .. 0x60ffffff : PSRAM (16MB) in mps2_common_init()
193 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); in mps2_common_init()
195 &mms->blockram, 0x01004000); in mps2_common_init()
197 &mms->blockram, 0x01008000); in mps2_common_init()
199 &mms->blockram, 0x0100c000); in mps2_common_init()
206 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); in mps2_common_init()
207 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); in mps2_common_init()
208 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); in mps2_common_init()
210 &mms->ssram23, 0x20400000); in mps2_common_init()
213 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); in mps2_common_init()
214 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); in mps2_common_init()
215 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); in mps2_common_init()
216 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); in mps2_common_init()
244 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); in mps2_common_init()
245 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); in mps2_common_init()
246 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); in mps2_common_init()
247 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); in mps2_common_init()
248 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); in mps2_common_init()
249 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); in mps2_common_init()
254 create_unimplemented_device("CMSDK APB peripheral region @0x40000000", in mps2_common_init()
255 0x40000000, 0x00010000); in mps2_common_init()
256 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", in mps2_common_init()
257 0x40010000, 0x00010000); in mps2_common_init()
258 create_unimplemented_device("Extra peripheral region @0x40020000", in mps2_common_init()
259 0x40020000, 0x00010000); in mps2_common_init()
261 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); in mps2_common_init()
262 create_unimplemented_device("VGA", 0x41000000, 0x0200000); in mps2_common_init()
269 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. in mps2_common_init()
279 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); in mps2_common_init()
281 for (i = 0; i < 5; i++) { in mps2_common_init()
285 static const hwaddr uartbase[] = {0x40004000, 0x40005000, in mps2_common_init()
286 0x40006000, 0x40007000, in mps2_common_init()
287 0x40009000}; in mps2_common_init()
289 static const int uartirq[] = {0, 2, 4, 18, 20}; in mps2_common_init()
302 sysbus_mmio_map(s, 0, uartbase[i]); in mps2_common_init()
303 sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1)); in mps2_common_init()
322 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); in mps2_common_init()
324 for (i = 0; i < 5; i++) { in mps2_common_init()
326 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; in mps2_common_init()
327 static const hwaddr uartbase[] = {0x40004000, 0x40005000, in mps2_common_init()
328 0x4002c000, 0x4002d000, in mps2_common_init()
329 0x4002e000}; in mps2_common_init()
338 qdev_connect_gpio_out(txrx_orgate_dev, 0, in mps2_common_init()
346 sysbus_mmio_map(s, 0, uartbase[i]); in mps2_common_init()
347 sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0)); in mps2_common_init()
357 for (i = 0; i < 4; i++) { in mps2_common_init()
358 static const hwaddr gpiobase[] = {0x40010000, 0x40011000, in mps2_common_init()
359 0x40012000, 0x40013000}; in mps2_common_init()
360 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); in mps2_common_init()
364 for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { in mps2_common_init()
366 hwaddr base = 0x40000000 + i * 0x1000; in mps2_common_init()
375 sysbus_mmio_map(sbd, 0, base); in mps2_common_init()
376 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); in mps2_common_init()
383 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, in mps2_common_init()
385 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); in mps2_common_init()
390 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, in mps2_common_init()
391 qdev_get_gpio_in_named(armv7m, "NMI", 0)); in mps2_common_init()
392 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); in mps2_common_init()
397 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in mps2_common_init()
398 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in mps2_common_init()
408 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); in mps2_common_init()
413 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); in mps2_common_init()
414 sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */ in mps2_common_init()
416 for (i = 0; i < 2; i++) { in mps2_common_init()
418 static const hwaddr spibase[] = {0x40020000, /* APB */ in mps2_common_init()
419 0x40021000, /* LCD */ in mps2_common_init()
420 0x40026000, /* Shield0 */ in mps2_common_init()
421 0x40027000}; /* Shield1 */ in mps2_common_init()
430 qdev_connect_gpio_out(orgate_dev, 0, in mps2_common_init()
432 for (j = 0; j < 2; j++) { in mps2_common_init()
437 for (i = 0; i < 4; i++) { in mps2_common_init()
438 static const hwaddr i2cbase[] = {0x40022000, /* Touch */ in mps2_common_init()
439 0x40023000, /* Audio */ in mps2_common_init()
440 0x40029000, /* Shield0 */ in mps2_common_init()
441 0x4002a000}; /* Shield1 */ in mps2_common_init()
454 create_unimplemented_device("i2s", 0x40024000, 0x400); in mps2_common_init()
464 0, 0x400000); in mps2_common_init()
490 mmc->scc_id = 0x41043850; in mps2_an385_class_init()
491 mmc->psram_base = 0x21000000; in mps2_an385_class_init()
492 mmc->ethernet_base = 0x40200000; in mps2_an385_class_init()
509 mmc->scc_id = 0x41043860; in mps2_an386_class_init()
510 mmc->psram_base = 0x21000000; in mps2_an386_class_init()
511 mmc->ethernet_base = 0x40200000; in mps2_an386_class_init()
528 mmc->scc_id = 0x41045000; in mps2_an500_class_init()
529 mmc->psram_base = 0x60000000; in mps2_an500_class_init()
530 mmc->ethernet_base = 0xa0000000; in mps2_an500_class_init()
547 mmc->scc_id = 0x41045110; in mps2_an511_class_init()
548 mmc->psram_base = 0x21000000; in mps2_an511_class_init()
549 mmc->ethernet_base = 0x40200000; in mps2_an511_class_init()