Lines Matching +full:usb +full:- +full:isp1763
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
52 #include "qemu/error-report.h"
55 #include "hw/or-irq.h"
57 #include "exec/address-spaces.h"
61 #include "hw/char/cmsdk-apb-uart.h"
62 #include "hw/timer/cmsdk-apb-timer.h"
63 #include "hw/misc/mps2-scc.h"
64 #include "hw/misc/mps2-fpgaio.h"
65 #include "hw/misc/tz-mpc.h"
66 #include "hw/misc/tz-msc.h"
74 #include "hw/core/split-irq.h"
75 #include "hw/qdev-clock.h"
92 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
93 * -1 means "use the system RAM".
99 int mpc; /* MPC number, -1 for "not behind an MPC" */
108 * IS_ROM: this RAM area is read-only
126 uint32_t init_svtor; /* init-svtor setting for SSE */
154 UnimplementedDeviceState usb; member
171 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
172 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
173 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
174 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
182 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
210 .name = "ssram-0",
216 .name = "ssram-1",
222 .name = "ssram-2",
228 .name = "ssram-0-alias",
239 .mpc = -1,
240 .mrindex = -1,
269 .mrindex = -1,
285 .mpc = -1,
300 .mrindex = -1,
312 for (p = mmc->raminfo; p->name; p++) { in find_raminfo_for_mpc()
313 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { in find_raminfo_for_mpc()
330 if (raminfo->mrindex < 0) { in mr_for_raminfo()
333 assert(!(raminfo->flags & IS_ROM)); in mr_for_raminfo()
334 return machine->ram; in mr_for_raminfo()
337 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); in mr_for_raminfo()
338 ram = &mms->ram[raminfo->mrindex]; in mr_for_raminfo()
340 memory_region_init_ram(ram, NULL, raminfo->name, in mr_for_raminfo()
341 raminfo->size, &error_fatal); in mr_for_raminfo()
342 if (raminfo->flags & IS_ROM) { in mr_for_raminfo()
364 * external-to-the-SSE interrupt is 32. in get_sse_irq_in()
369 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); in get_sse_irq_in()
373 * documentation) to the SSE external-interrupt number. in get_sse_irq_in()
375 irqno -= 32; in get_sse_irq_in()
377 if (mc->max_cpus > 1) { in get_sse_irq_in()
378 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); in get_sse_irq_in()
380 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); in get_sse_irq_in()
384 /* Union describing the device-specific extra data we pass to the devfn. */
408 PPCExtraData extradata; /* to pass device-specific info to the devfn */
441 int i = uart - &mms->uart[0]; in make_uart()
443 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); in make_uart()
447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); in make_uart()
470 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); in make_scc()
471 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in make_scc()
472 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in make_scc()
473 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); in make_scc()
476 for (i = 0; i < mmc->len_oscclk; i++) { in make_scc()
477 qlist_append_int(oscclk, mmc->oscclk[i]); in make_scc()
493 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); in make_fpgaio()
494 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); in make_fpgaio()
495 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); in make_fpgaio()
508 * except that it doesn't support the checksum-offload feature. in make_eth_dev()
510 mms->lan9118 = qdev_new(TYPE_LAN9118); in make_eth_dev()
511 qemu_configure_nic_device(mms->lan9118, true, NULL); in make_eth_dev()
513 s = SYS_BUS_DEVICE(mms->lan9118); in make_eth_dev()
525 * The AN524 makes the ethernet and USB share a PPC port. in make_eth_usb()
530 memory_region_init(&mms->eth_usb_container, OBJECT(mms), in make_eth_usb()
531 "mps2-tz-eth-usb-container", 0x200000); in make_eth_usb()
535 * except that it doesn't support the checksum-offload feature. in make_eth_usb()
537 mms->lan9118 = qdev_new(TYPE_LAN9118); in make_eth_usb()
538 qemu_configure_nic_device(mms->lan9118, true, NULL); in make_eth_usb()
540 s = SYS_BUS_DEVICE(mms->lan9118); in make_eth_usb()
544 memory_region_add_subregion(&mms->eth_usb_container, in make_eth_usb()
547 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ in make_eth_usb()
548 object_initialize_child(OBJECT(mms), "usb-otg", in make_eth_usb()
549 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); in make_eth_usb()
550 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); in make_eth_usb()
551 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); in make_eth_usb()
552 s = SYS_BUS_DEVICE(&mms->usb); in make_eth_usb()
555 memory_region_add_subregion(&mms->eth_usb_container, in make_eth_usb()
558 return &mms->eth_usb_container; in make_eth_usb()
566 int i = mpc - &mms->mpc[0]; in make_mpc()
577 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); in make_mpc()
580 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), in make_mpc()
595 return mms->remap ? 0x28000000 : 0; in boot_mem_base()
611 if (mmc->fpga_type != FPGA_AN524) { in remap_memory()
617 TZMPC *mpc = &mms->mpc[i]; in remap_memory()
639 int i = dma - &mms->dma[0]; in make_dma()
641 char *mscname = g_strdup_printf("%s-msc", name); in make_dma()
642 TZMSC *msc = &mms->msc[i]; in make_dma()
643 DeviceState *iotkitdev = DEVICE(&mms->iotkit); in make_dma()
654 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); in make_dma()
669 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), in make_dma()
670 ARRAY_SIZE(mms->ppc) + i, in make_dma()
724 * If this is an internal-use-only i2c bus, mark it full in make_i2c()
725 * so that user-created i2c devices are not plugged into it. in make_i2c()
726 * If we implement models of any on-board i2c devices that in make_i2c()
727 * plug in to one of the internal-use-only buses, then we will in make_i2c()
731 if (extradata->i2c_internal) { in make_i2c()
765 for (p = mmc->raminfo; p->name; p++) { in create_non_mpc_ram()
766 if (p->flags & IS_ALIAS) { in create_non_mpc_ram()
767 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); in create_non_mpc_ram()
769 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); in create_non_mpc_ram()
770 } else if (p->mpc == -1) { in create_non_mpc_ram()
773 memory_region_add_subregion(get_system_memory(), p->base, mr); in create_non_mpc_ram()
785 * Use a per-board specification (for when the boot RAM is in in boot_ram_size()
788 if (mmc->boot_ram_size) { in boot_ram_size()
789 return mmc->boot_ram_size; in boot_ram_size()
792 for (p = mmc->raminfo; p->name; p++) { in boot_ram_size()
793 if (p->base == boot_mem_base(mms)) { in boot_ram_size()
794 return p->size; in boot_ram_size()
812 if (machine->ram_size != mc->default_ram_size) { in mps2tz_common_init()
813 char *sz = size_to_str(mc->default_ram_size); in mps2tz_common_init()
819 /* These clocks don't need migration because they are fixed-frequency */ in mps2tz_common_init()
820 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); in mps2tz_common_init()
821 clock_set_hz(mms->sysclk, mmc->sysclk_frq); in mps2tz_common_init()
822 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); in mps2tz_common_init()
823 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); in mps2tz_common_init()
825 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, in mps2tz_common_init()
826 mmc->armsse_type); in mps2tz_common_init()
827 iotkitdev = DEVICE(&mms->iotkit); in mps2tz_common_init()
828 object_property_set_link(OBJECT(&mms->iotkit), "memory", in mps2tz_common_init()
830 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); in mps2tz_common_init()
831 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); in mps2tz_common_init()
832 if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { in mps2tz_common_init()
833 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); in mps2tz_common_init()
835 if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { in mps2tz_common_init()
836 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); in mps2tz_common_init()
839 if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { in mps2tz_common_init()
840 qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); in mps2tz_common_init()
842 if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { in mps2tz_common_init()
843 qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); in mps2tz_common_init()
846 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); in mps2tz_common_init()
847 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); in mps2tz_common_init()
848 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); in mps2tz_common_init()
849 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); in mps2tz_common_init()
857 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); in mps2tz_common_init()
858 if (mc->max_cpus > 1) { in mps2tz_common_init()
859 for (i = 0; i < mmc->numirq; i++) { in mps2tz_common_init()
860 char *name = g_strdup_printf("mps2-irq-splitter%d", i); in mps2tz_common_init()
861 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; in mps2tz_common_init()
869 object_property_set_int(OBJECT(splitter), "num-lines", 2, in mps2tz_common_init()
873 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), in mps2tz_common_init()
876 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), in mps2tz_common_init()
884 object_initialize_child(OBJECT(machine), "sec-resp-splitter", in mps2tz_common_init()
885 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); in mps2tz_common_init()
886 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", in mps2tz_common_init()
887 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), in mps2tz_common_init()
889 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); in mps2tz_common_init()
890 dev_splitter = DEVICE(&mms->sec_resp_splitter); in mps2tz_common_init()
896 * the aliases between secure and non-secure regions in the in mps2tz_common_init()
912 * those inputs are never wired up and are treated as always-zero.) in mps2tz_common_init()
914 object_initialize_child(OBJECT(mms), "uart-irq-orgate", in mps2tz_common_init()
915 &mms->uart_irq_orgate, TYPE_OR_IRQ); in mps2tz_common_init()
916 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", in mps2tz_common_init()
917 2 * ARRAY_SIZE(mms->uart), in mps2tz_common_init()
919 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); in mps2tz_common_init()
920 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, in mps2tz_common_init()
921 get_sse_irq_in(mms, mmc->uart_overflow_irq)); in mps2tz_common_init()
937 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, in mps2tz_common_init()
938 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, in mps2tz_common_init()
939 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, in mps2tz_common_init()
944 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, in mps2tz_common_init()
945 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, in mps2tz_common_init()
946 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, in mps2tz_common_init()
947 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, in mps2tz_common_init()
948 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, in mps2tz_common_init()
949 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, in mps2tz_common_init()
950 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, in mps2tz_common_init()
951 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, in mps2tz_common_init()
952 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, in mps2tz_common_init()
953 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, in mps2tz_common_init()
954 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000, {}, in mps2tz_common_init()
956 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000, {}, in mps2tz_common_init()
958 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000, {}, in mps2tz_common_init()
960 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000, {}, in mps2tz_common_init()
966 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, in mps2tz_common_init()
967 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, in mps2tz_common_init()
969 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, in mps2tz_common_init()
974 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, in mps2tz_common_init()
975 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, in mps2tz_common_init()
976 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, in mps2tz_common_init()
977 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, in mps2tz_common_init()
978 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, in mps2tz_common_init()
984 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, in mps2tz_common_init()
985 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, in mps2tz_common_init()
986 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, in mps2tz_common_init()
987 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, in mps2tz_common_init()
995 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, in mps2tz_common_init()
996 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, in mps2tz_common_init()
997 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, in mps2tz_common_init()
1002 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000, {}, in mps2tz_common_init()
1004 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000, {}, in mps2tz_common_init()
1006 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, in mps2tz_common_init()
1007 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, in mps2tz_common_init()
1008 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, in mps2tz_common_init()
1009 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000, {}, in mps2tz_common_init()
1011 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000, {}, in mps2tz_common_init()
1014 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000, {}, in mps2tz_common_init()
1020 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, in mps2tz_common_init()
1021 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, in mps2tz_common_init()
1023 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, in mps2tz_common_init()
1024 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, in mps2tz_common_init()
1025 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, in mps2tz_common_init()
1026 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, in mps2tz_common_init()
1027 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, in mps2tz_common_init()
1028 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, in mps2tz_common_init()
1029 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, in mps2tz_common_init()
1032 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, in mps2tz_common_init()
1033 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, in mps2tz_common_init()
1038 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, in mps2tz_common_init()
1039 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, in mps2tz_common_init()
1040 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, in mps2tz_common_init()
1041 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, in mps2tz_common_init()
1042 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, in mps2tz_common_init()
1050 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, in mps2tz_common_init()
1051 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, in mps2tz_common_init()
1052 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, in mps2tz_common_init()
1057 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, in mps2tz_common_init()
1059 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, in mps2tz_common_init()
1061 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, in mps2tz_common_init()
1062 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, in mps2tz_common_init()
1063 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, in mps2tz_common_init()
1064 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, in mps2tz_common_init()
1066 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, in mps2tz_common_init()
1069 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, in mps2tz_common_init()
1075 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, in mps2tz_common_init()
1076 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, in mps2tz_common_init()
1077 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, in mps2tz_common_init()
1078 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, in mps2tz_common_init()
1079 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, in mps2tz_common_init()
1080 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, in mps2tz_common_init()
1081 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, in mps2tz_common_init()
1082 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, in mps2tz_common_init()
1083 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, in mps2tz_common_init()
1086 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, in mps2tz_common_init()
1087 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, in mps2tz_common_init()
1092 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, in mps2tz_common_init()
1093 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, in mps2tz_common_init()
1094 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, in mps2tz_common_init()
1095 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, in mps2tz_common_init()
1100 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, in mps2tz_common_init()
1105 switch (mmc->fpga_type) { in mps2tz_common_init()
1125 TZPPC *ppc = &mms->ppc[i]; in mps2tz_common_init()
1130 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, in mps2tz_common_init()
1135 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; in mps2tz_common_init()
1139 if (!pinfo->devfn) { in mps2tz_common_init()
1143 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, in mps2tz_common_init()
1144 pinfo->irqs, &pinfo->extradata); in mps2tz_common_init()
1154 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; in mps2tz_common_init()
1156 if (!pinfo->devfn) { in mps2tz_common_init()
1159 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); in mps2tz_common_init()
1161 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); in mps2tz_common_init()
1167 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); in mps2tz_common_init()
1174 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); in mps2tz_common_init()
1179 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); in mps2tz_common_init()
1184 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); in mps2tz_common_init()
1197 if (mmc->fpga_type == FPGA_AN547) { in mps2tz_common_init()
1204 if (mmc->fpga_type == FPGA_AN524) { in mps2tz_common_init()
1209 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); in mps2tz_common_init()
1210 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, in mps2tz_common_init()
1211 mms->remap_irq); in mps2tz_common_init()
1214 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, in mps2tz_common_init()
1239 const char *val = mms->remap ? "QSPI" : "BRAM"; in mps2_get_remap()
1248 mms->remap = false; in mps2_set_remap()
1250 mms->remap = true; in mps2_set_remap()
1266 remap_memory(mms, mms->remap); in mps2_machine_reset()
1276 mc->init = mps2tz_common_init; in mps2tz_class_init()
1277 mc->reset = mps2_machine_reset; in mps2tz_class_init()
1278 iic->check = mps2_tz_idau_check; in mps2tz_class_init()
1281 mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; in mps2tz_class_init()
1282 mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; in mps2tz_class_init()
1283 mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; in mps2tz_class_init()
1284 mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; in mps2tz_class_init()
1290 * Set mc->default_ram_size and default_ram_id from the in mps2tz_set_default_ram_info()
1291 * information in mmc->raminfo. in mps2tz_set_default_ram_info()
1296 for (p = mmc->raminfo; p->name; p++) { in mps2tz_set_default_ram_info()
1297 if (p->mrindex < 0) { in mps2tz_set_default_ram_info()
1299 mc->default_ram_size = p->size; in mps2tz_set_default_ram_info()
1300 mc->default_ram_id = p->name; in mps2tz_set_default_ram_info()
1312 ARM_CPU_TYPE_NAME("cortex-m33"), in mps2tz_an505_class_init()
1316 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; in mps2tz_an505_class_init()
1317 mc->default_cpus = 1; in mps2tz_an505_class_init()
1318 mc->min_cpus = mc->default_cpus; in mps2tz_an505_class_init()
1319 mc->max_cpus = mc->default_cpus; in mps2tz_an505_class_init()
1320 mmc->fpga_type = FPGA_AN505; in mps2tz_an505_class_init()
1321 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); in mps2tz_an505_class_init()
1322 mc->valid_cpu_types = valid_cpu_types; in mps2tz_an505_class_init()
1323 mmc->scc_id = 0x41045050; in mps2tz_an505_class_init()
1324 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ in mps2tz_an505_class_init()
1325 mmc->apb_periph_frq = mmc->sysclk_frq; in mps2tz_an505_class_init()
1326 mmc->oscclk = an505_oscclk; in mps2tz_an505_class_init()
1327 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); in mps2tz_an505_class_init()
1328 mmc->fpgaio_num_leds = 2; in mps2tz_an505_class_init()
1329 mmc->fpgaio_has_switches = false; in mps2tz_an505_class_init()
1330 mmc->fpgaio_has_dbgctrl = false; in mps2tz_an505_class_init()
1331 mmc->numirq = 92; in mps2tz_an505_class_init()
1332 mmc->uart_overflow_irq = 47; in mps2tz_an505_class_init()
1333 mmc->init_svtor = 0x10000000; in mps2tz_an505_class_init()
1334 mmc->sram_addr_width = 15; in mps2tz_an505_class_init()
1335 mmc->raminfo = an505_raminfo; in mps2tz_an505_class_init()
1336 mmc->armsse_type = TYPE_IOTKIT; in mps2tz_an505_class_init()
1337 mmc->boot_ram_size = 0; in mps2tz_an505_class_init()
1346 ARM_CPU_TYPE_NAME("cortex-m33"), in mps2tz_an521_class_init()
1350 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; in mps2tz_an521_class_init()
1351 mc->default_cpus = 2; in mps2tz_an521_class_init()
1352 mc->min_cpus = mc->default_cpus; in mps2tz_an521_class_init()
1353 mc->max_cpus = mc->default_cpus; in mps2tz_an521_class_init()
1354 mmc->fpga_type = FPGA_AN521; in mps2tz_an521_class_init()
1355 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); in mps2tz_an521_class_init()
1356 mc->valid_cpu_types = valid_cpu_types; in mps2tz_an521_class_init()
1357 mmc->scc_id = 0x41045210; in mps2tz_an521_class_init()
1358 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ in mps2tz_an521_class_init()
1359 mmc->apb_periph_frq = mmc->sysclk_frq; in mps2tz_an521_class_init()
1360 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ in mps2tz_an521_class_init()
1361 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); in mps2tz_an521_class_init()
1362 mmc->fpgaio_num_leds = 2; in mps2tz_an521_class_init()
1363 mmc->fpgaio_has_switches = false; in mps2tz_an521_class_init()
1364 mmc->fpgaio_has_dbgctrl = false; in mps2tz_an521_class_init()
1365 mmc->numirq = 92; in mps2tz_an521_class_init()
1366 mmc->uart_overflow_irq = 47; in mps2tz_an521_class_init()
1367 mmc->init_svtor = 0x10000000; in mps2tz_an521_class_init()
1368 mmc->sram_addr_width = 15; in mps2tz_an521_class_init()
1369 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ in mps2tz_an521_class_init()
1370 mmc->armsse_type = TYPE_SSE200; in mps2tz_an521_class_init()
1371 mmc->boot_ram_size = 0; in mps2tz_an521_class_init()
1380 ARM_CPU_TYPE_NAME("cortex-m33"), in mps3tz_an524_class_init()
1384 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; in mps3tz_an524_class_init()
1385 mc->default_cpus = 2; in mps3tz_an524_class_init()
1386 mc->min_cpus = mc->default_cpus; in mps3tz_an524_class_init()
1387 mc->max_cpus = mc->default_cpus; in mps3tz_an524_class_init()
1388 mmc->fpga_type = FPGA_AN524; in mps3tz_an524_class_init()
1389 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); in mps3tz_an524_class_init()
1390 mc->valid_cpu_types = valid_cpu_types; in mps3tz_an524_class_init()
1391 mmc->scc_id = 0x41045240; in mps3tz_an524_class_init()
1392 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ in mps3tz_an524_class_init()
1393 mmc->apb_periph_frq = mmc->sysclk_frq; in mps3tz_an524_class_init()
1394 mmc->oscclk = an524_oscclk; in mps3tz_an524_class_init()
1395 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); in mps3tz_an524_class_init()
1396 mmc->fpgaio_num_leds = 10; in mps3tz_an524_class_init()
1397 mmc->fpgaio_has_switches = true; in mps3tz_an524_class_init()
1398 mmc->fpgaio_has_dbgctrl = false; in mps3tz_an524_class_init()
1399 mmc->numirq = 95; in mps3tz_an524_class_init()
1400 mmc->uart_overflow_irq = 47; in mps3tz_an524_class_init()
1401 mmc->init_svtor = 0x10000000; in mps3tz_an524_class_init()
1402 mmc->sram_addr_width = 15; in mps3tz_an524_class_init()
1403 mmc->raminfo = an524_raminfo; in mps3tz_an524_class_init()
1404 mmc->armsse_type = TYPE_SSE200; in mps3tz_an524_class_init()
1405 mmc->boot_ram_size = 0; in mps3tz_an524_class_init()
1419 ARM_CPU_TYPE_NAME("cortex-m55"), in mps3tz_an547_class_init()
1423 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; in mps3tz_an547_class_init()
1424 mc->default_cpus = 1; in mps3tz_an547_class_init()
1425 mc->min_cpus = mc->default_cpus; in mps3tz_an547_class_init()
1426 mc->max_cpus = mc->default_cpus; in mps3tz_an547_class_init()
1427 mmc->fpga_type = FPGA_AN547; in mps3tz_an547_class_init()
1428 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); in mps3tz_an547_class_init()
1429 mc->valid_cpu_types = valid_cpu_types; in mps3tz_an547_class_init()
1430 mmc->scc_id = 0x41055470; in mps3tz_an547_class_init()
1431 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ in mps3tz_an547_class_init()
1432 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ in mps3tz_an547_class_init()
1433 mmc->oscclk = an524_oscclk; /* same as AN524 */ in mps3tz_an547_class_init()
1434 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); in mps3tz_an547_class_init()
1435 mmc->fpgaio_num_leds = 10; in mps3tz_an547_class_init()
1436 mmc->fpgaio_has_switches = true; in mps3tz_an547_class_init()
1437 mmc->fpgaio_has_dbgctrl = true; in mps3tz_an547_class_init()
1438 mmc->numirq = 96; in mps3tz_an547_class_init()
1439 mmc->uart_overflow_irq = 48; in mps3tz_an547_class_init()
1440 mmc->init_svtor = 0x00000000; in mps3tz_an547_class_init()
1441 mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; in mps3tz_an547_class_init()
1442 mmc->sram_addr_width = 21; in mps3tz_an547_class_init()
1443 mmc->raminfo = an547_raminfo; in mps3tz_an547_class_init()
1444 mmc->armsse_type = TYPE_SSE300; in mps3tz_an547_class_init()
1445 mmc->boot_ram_size = 512 * KiB; in mps3tz_an547_class_init()