Lines Matching +full:0 +full:x13800000
41 #define EXYNOS4210_CHIPID_ADDR 0x10000000
44 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
47 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000
50 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000
53 #define EXYNOS4210_I2C_SHIFT 0x00010000
54 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000
60 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000
61 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000
62 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000
63 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000
72 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
73 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
76 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
77 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
80 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080
81 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
83 0x00010000 * (n))
87 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000
90 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000
93 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400
96 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
99 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
102 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
103 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
104 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
201 { 0, EXT_GIC_ID_MDMA_LCD0 },
236 { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
264 * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
265 * wired to anything so we can use 0 as a terminator.
268 #define IRQNONE 0
274 { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
275 { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
276 { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
277 { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
284 { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
305 for (i = 0; i < COMBINERMAP_SIZE; i++) { in combinermap_entry()
306 if (combinermap[i][0] == irq) { in combinermap_entry()
316 int i = 0; in mapline_size()
339 int splitcount = 0; in exynos4210_init_board_irqs()
344 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { in exynos4210_init_board_irqs()
345 irq_id = 0; in exynos4210_init_board_irqs()
378 splitin = 0; in exynos4210_init_board_irqs()
380 s->irq_table[in] = qdev_get_gpio_in(splitter, 0); in exynos4210_init_board_irqs()
421 s->irq_table[n] = qdev_get_gpio_in(splitter, 0); in exynos4210_init_board_irqs()
422 qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); in exynos4210_init_board_irqs()
448 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
449 0x09, 0x00, 0x00, 0x00 };
478 0xe59f3034, /* ldr r3, External gic_cpu_if */ in exynos4210_write_secondary()
479 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ in exynos4210_write_secondary()
480 0xe59f0034, /* ldr r0, startaddr */ in exynos4210_write_secondary()
481 0xe3a01001, /* mov r1, #1 */ in exynos4210_write_secondary()
482 0xe5821000, /* str r1, [r2] */ in exynos4210_write_secondary()
483 0xe5831000, /* str r1, [r3] */ in exynos4210_write_secondary()
484 0xe3a010ff, /* mov r1, #0xff */ in exynos4210_write_secondary()
485 0xe5821004, /* str r1, [r2, #4] */ in exynos4210_write_secondary()
486 0xe5831004, /* str r1, [r3, #4] */ in exynos4210_write_secondary()
487 0xf57ff04f, /* dsb */ in exynos4210_write_secondary()
488 0xe320f003, /* wfi */ in exynos4210_write_secondary()
489 0xe5901000, /* ldr r1, [r0] */ in exynos4210_write_secondary()
490 0xe1110001, /* tst r1, r1 */ in exynos4210_write_secondary()
491 0x0afffffb, /* beq <wfi> */ in exynos4210_write_secondary()
492 0xe12fff11, /* bx r1 */ in exynos4210_write_secondary()
494 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ in exynos4210_write_secondary()
495 0 /* bootreg: Boot register address is held here */ in exynos4210_write_secondary()
499 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { in exynos4210_write_secondary()
508 /* Exynos4210 has 0x9 as cluster ID */ in exynos4210_calc_affinity()
509 return (0x9 << ARM_AFF1_SHIFT) | cpu; in exynos4210_calc_affinity()
535 sysbus_mmio_map(busdev, 0, base); in pl330_create()
541 for (i = 0; i < nevents + 1; i++) { in pl330_create()
544 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); in pl330_create()
556 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
577 for (i = 0; i < EXYNOS4210_NCPUS; i++) { in exynos4210_realize()
583 qdev_connect_gpio_out(orgate, 0, in exynos4210_realize()
591 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); in exynos4210_realize()
592 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
594 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); in exynos4210_realize()
605 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); in exynos4210_realize()
608 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
616 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { in exynos4210_realize()
620 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); in exynos4210_realize()
626 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { in exynos4210_realize()
629 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); in exynos4210_realize()
650 "exynos4210.irom_alias", &s->irom_mem, 0, in exynos4210_realize()
672 s->irq_table[exynos4210_get_irq(22, 0)], in exynos4210_realize()
680 s->irq_table[exynos4210_get_irq(23, 0)], in exynos4210_realize()
688 for (n = 0; n < 4; n++) { in exynos4210_realize()
695 s->irq_table[exynos4210_get_irq(51, 0)]); in exynos4210_realize()
698 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); in exynos4210_realize()
701 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { in exynos4210_realize()
714 sysbus_connect_irq(busdev, 0, i2c_irq); in exynos4210_realize()
715 sysbus_mmio_map(busdev, 0, addr); in exynos4210_realize()
721 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, in exynos4210_realize()
722 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), in exynos4210_realize()
723 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); in exynos4210_realize()
738 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { in exynos4210_realize()
760 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); in exynos4210_realize()
761 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); in exynos4210_realize()
763 di = drive_get(IF_SD, 0, n); in exynos4210_realize()
777 sysbus_mmio_map(busdev, 0, EXYNOS4210_FIMD0_BASE_ADDR); in exynos4210_realize()
778 for (n = 0; n < 3; n++) { in exynos4210_realize()
786 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, in exynos4210_realize()
787 &s->pl330_irq_orgate[0], in exynos4210_realize()
788 s->irq_table[exynos4210_get_irq(21, 0)], in exynos4210_realize()
799 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, in exynos4210_realize()
800 qdev_get_gpio_in(pl330[0], 15)); in exynos4210_realize()
804 qdev_get_gpio_in(pl330[0], 17)); in exynos4210_realize()
814 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { in exynos4210_init()
822 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { in exynos4210_init()
827 for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { in exynos4210_init()