Lines Matching full:196
182 [ASPEED_DEV_PCIE2] = 196,
183 [ASPEED_DEV_UART0] = 196,
184 [ASPEED_DEV_UART1] = 196,
185 [ASPEED_DEV_UART2] = 196,
186 [ASPEED_DEV_UART3] = 196,
187 [ASPEED_DEV_UART5] = 196,
188 [ASPEED_DEV_UART6] = 196,
189 [ASPEED_DEV_UART7] = 196,
190 [ASPEED_DEV_UART8] = 196,
191 [ASPEED_DEV_UART9] = 196,
192 [ASPEED_DEV_UART10] = 196,
193 [ASPEED_DEV_UART11] = 196,
194 [ASPEED_DEV_UART12] = 196,
195 [ASPEED_DEV_ETH1] = 196,
196 [ASPEED_DEV_ETH2] = 196,
197 [ASPEED_DEV_ETH3] = 196,
231 /* GICINT 196 */
274 {196, 1, 4, ast2700_gic132_gic196_intcmap},