Lines Matching +full:cpu +full:- +full:to +full:- +full:pci
13 #include "hw/pci/pci_host.h"
14 #include "cpu.h"
19 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
20 #define TYPE_TYPHOON_IOMMU_MEMORY_REGION "typhoon-iommu-memory-region"
28 AlphaCPU *cpu[4]; member
62 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) in cpu_irq_change() argument
64 /* If there are any non-masked interrupts, tell the cpu. */ in cpu_irq_change()
65 if (cpu != NULL) { in cpu_irq_change()
66 CPUState *cs = CPU(cpu); in cpu_irq_change()
79 CPUState *cpu = current_cpu; in cchip_read() local
92 /* All sorts of stuff related to real DRAM. */ in cchip_read()
97 ret = s->cchip.misc | (cpu->cpu_index & 3); in cchip_read()
114 ret = s->cchip.dim[0]; in cchip_read()
118 ret = s->cchip.dim[1]; in cchip_read()
122 ret = s->cchip.dim[0] & s->cchip.drir; in cchip_read()
126 ret = s->cchip.dim[1] & s->cchip.drir; in cchip_read()
130 ret = s->cchip.drir; in cchip_read()
139 ret = s->cchip.iic[0]; in cchip_read()
143 ret = s->cchip.iic[1]; in cchip_read()
155 /* All sorts of stuff related to interrupt delivery timings. */ in cchip_read()
163 ret = s->cchip.dim[2]; in cchip_read()
167 ret = s->cchip.dim[3]; in cchip_read()
171 ret = s->cchip.dim[2] & s->cchip.drir; in cchip_read()
175 ret = s->cchip.dim[3] & s->cchip.drir; in cchip_read()
180 ret = s->cchip.iic[2]; in cchip_read()
184 ret = s->cchip.iic[3]; in cchip_read()
207 /* Skip this. It's all related to DRAM timing and setup. */ in dchip_read()
220 ret = s->pchip.win[0].wba; in pchip_read()
224 ret = s->pchip.win[1].wba; in pchip_read()
228 ret = s->pchip.win[2].wba; in pchip_read()
232 ret = s->pchip.win[3].wba; in pchip_read()
237 ret = s->pchip.win[0].wsm; in pchip_read()
241 ret = s->pchip.win[1].wsm; in pchip_read()
245 ret = s->pchip.win[2].wsm; in pchip_read()
249 ret = s->pchip.win[3].wsm; in pchip_read()
254 ret = s->pchip.win[0].tba; in pchip_read()
258 ret = s->pchip.win[1].tba; in pchip_read()
262 ret = s->pchip.win[2].tba; in pchip_read()
266 ret = s->pchip.win[3].tba; in pchip_read()
271 ret = s->pchip.ctl; in pchip_read()
319 /* All sorts of stuff related to real DRAM. */ in cchip_write()
324 newval = oldval = s->cchip.misc; in cchip_write()
338 s->cchip.misc = newval; in cchip_write()
340 /* Pass on changes to IPI and ITI state. */ in cchip_write()
344 AlphaCPU *cpu = s->cchip.cpu[i]; in cchip_write() local
345 if (cpu != NULL) { in cchip_write()
346 CPUState *cs = CPU(cpu); in cchip_write()
377 s->cchip.dim[0] = val; in cchip_write()
378 cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir); in cchip_write()
382 s->cchip.dim[1] = val; in cchip_write()
383 cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir); in cchip_write()
396 s->cchip.iic[0] = val & 0xffffff; in cchip_write()
399 s->cchip.iic[1] = val & 0xffffff; in cchip_write()
411 /* All sorts of stuff related to interrupt delivery timings. */ in cchip_write()
419 s->cchip.dim[2] = val; in cchip_write()
420 cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir); in cchip_write()
424 s->cchip.dim[3] = val; in cchip_write()
425 cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir); in cchip_write()
433 s->cchip.iic[2] = val & 0xffffff; in cchip_write()
436 s->cchip.iic[3] = val & 0xffffff; in cchip_write()
459 /* Skip this. It's all related to DRAM timing and setup. */ in dchip_write()
472 s->pchip.win[0].wba = val & 0xfff00003u; in pchip_write()
476 s->pchip.win[1].wba = val & 0xfff00003u; in pchip_write()
480 s->pchip.win[2].wba = val & 0xfff00003u; in pchip_write()
484 s->pchip.win[3].wba = (val & 0x80fff00001ull) | 2; in pchip_write()
489 s->pchip.win[0].wsm = val & 0xfff00000u; in pchip_write()
493 s->pchip.win[1].wsm = val & 0xfff00000u; in pchip_write()
497 s->pchip.win[2].wsm = val & 0xfff00000u; in pchip_write()
501 s->pchip.win[3].wsm = val & 0xfff00000u; in pchip_write()
506 s->pchip.win[0].tba = val & 0x7fffffc00ull; in pchip_write()
510 s->pchip.win[1].tba = val & 0x7fffffc00ull; in pchip_write()
514 s->pchip.win[2].tba = val & 0x7fffffc00ull; in pchip_write()
518 s->pchip.win[3].tba = val & 0x7fffffc00ull; in pchip_write()
523 oldval = s->pchip.ctl; in pchip_write()
526 s->pchip.ctl = oldval; in pchip_write()
620 /* A subroutine of typhoon_translate_iommu that handles scatter-gather
636 four single-address-cycle translation windows. */
640 uint32_t wba = win->wba; in window_translate()
641 uint64_t wsm = win->wsm; in window_translate()
642 uint64_t tba = win->tba; in window_translate()
656 /* Scatter-gather translation. */ in window_translate()
659 /* See table 10-6, Generating PTE address for PCI DMA Address. */ in window_translate()
664 /* Direct-mapped translation. */ in window_translate()
669 /* Handle PCI-to-system address translation. */
670 /* TODO: A translation failure here ought to set PCI error codes on the
682 /* Single-address cycle. */ in typhoon_translate_iommu()
685 if ((pchip->ctl & 0x20) in typhoon_translate_iommu()
693 if (window_translate(&pchip->win[i], addr, &ret)) { in typhoon_translate_iommu()
699 if ((pchip->win[3].wba & 0x80000000000ull) == 0 in typhoon_translate_iommu()
700 && window_translate(&pchip->win[3], addr, &ret)) { in typhoon_translate_iommu()
704 /* Double-address cycle. */ in typhoon_translate_iommu()
708 if (pchip->ctl & 0x40) { in typhoon_translate_iommu()
717 if ((pchip->win[3].wba & 0x80000000001ull) == 0x80000000001ull) { in typhoon_translate_iommu()
720 pte_addr = pchip->win[3].tba & 0x7ffc00000ull; in typhoon_translate_iommu()
738 return &s->pchip.iommu_as; in typhoon_pci_dma_iommu()
752 drir = s->cchip.drir; in typhoon_set_irq()
758 s->cchip.drir = drir; in typhoon_set_irq()
761 cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir); in typhoon_set_irq()
776 and so we don't have to worry about missing interrupts just in typhoon_set_timer_irq()
783 /* Deliver the interrupt to each CPU, considering each CPU's IIC. */ in typhoon_set_timer_irq()
785 AlphaCPU *cpu = s->cchip.cpu[i]; in typhoon_set_timer_irq() local
786 if (cpu != NULL) { in typhoon_set_timer_irq()
787 uint32_t iic = s->cchip.iic[i]; in typhoon_set_timer_irq()
794 interpretation that makes sense, and "allows the CPU to in typhoon_set_timer_irq()
798 iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000); in typhoon_set_timer_irq()
799 s->cchip.iic[i] = iic; in typhoon_set_timer_irq()
802 /* Set the ITI bit for this cpu. */ in typhoon_set_timer_irq()
803 s->cchip.misc |= 1 << (i + 4); in typhoon_set_timer_irq()
805 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER); in typhoon_set_timer_irq()
814 int cpu = (uintptr_t)opaque & 3; in typhoon_alarm_timer() local
816 /* Set the ITI bit for this cpu. */ in typhoon_alarm_timer()
817 s->cchip.misc |= 1 << (cpu + 4); in typhoon_alarm_timer()
818 cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); in typhoon_alarm_timer()
837 s->cchip.misc = 0x800000000ull; /* Revision: Typhoon. */ in typhoon_init()
838 s->pchip.win[3].wba = 2; /* Window 3 SG always enabled. */ in typhoon_init()
840 /* Remember the CPUs so that we can deliver interrupts to them. */ in typhoon_init()
842 AlphaCPU *cpu = cpus[i]; in typhoon_init() local
843 s->cchip.cpu[i] = cpu; in typhoon_init()
844 if (cpu != NULL) { in typhoon_init()
845 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in typhoon_init()
859 /* ??? The TIGbus is used for delivering interrupts, and access to in typhoon_init()
860 the flash ROM. I'm not sure that we need to implement it at all. */ in typhoon_init()
863 memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0", in typhoon_init()
866 &s->pchip.region); in typhoon_init()
869 memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0", in typhoon_init()
872 &s->cchip.region); in typhoon_init()
875 memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0", in typhoon_init()
878 &s->dchip_region); in typhoon_init()
880 /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ in typhoon_init()
881 memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4 * GiB); in typhoon_init()
883 &s->pchip.reg_mem); in typhoon_init()
885 /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */ in typhoon_init()
886 memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops, in typhoon_init()
887 NULL, "pci0-io", 32 * MiB); in typhoon_init()
889 &s->pchip.reg_io); in typhoon_init()
891 b = pci_register_root_bus(dev, "pci", in typhoon_init()
893 &s->pchip.reg_mem, &s->pchip.reg_io, in typhoon_init()
895 phb->bus = b; in typhoon_init()
898 /* Host memory as seen from the PCI side, via the IOMMU. */ in typhoon_init()
899 memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu), in typhoon_init()
901 "iommu-typhoon", UINT64_MAX); in typhoon_init()
902 address_space_init(&s->pchip.iommu_as, MEMORY_REGION(&s->pchip.iommu), in typhoon_init()
903 "pchip0-pci"); in typhoon_init()
906 /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ in typhoon_init()
907 memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, in typhoon_init()
908 b, "pci0-iack", 64 * MiB); in typhoon_init()
910 &s->pchip.reg_iack); in typhoon_init()
912 /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ in typhoon_init()
913 memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, in typhoon_init()
914 b, "pci0-conf", 16 * MiB); in typhoon_init()
916 &s->pchip.reg_conf); in typhoon_init()
918 /* For the record, these are the mappings for the second PCI bus. in typhoon_init()
921 /* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */ in typhoon_init()
923 /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */ in typhoon_init()
924 /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */ in typhoon_init()
925 /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */ in typhoon_init()
941 imrc->translate = typhoon_translate_iommu; in typhoon_iommu_memory_region_class_init()