qemu/fpu/softfloat-specialize.c.inc

5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
9  *  the SoftFloat-2a license
11  *  GPL-v2-or-later
14  * taken to be licensed under the Softfloat-2a license unless specifically
20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
26 National Science Foundation under grant MIP-9311980.  The original version
27 of this code was written as part of a project to build a fixed-point vector
79  * version 2 or later. See the COPYING file in the top-level directory.
89     return status->no_signaling_nans;
97  * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
105     return status->snan_bit_is_one;
113 /*----------------------------------------------------------------------------
114 | For the deconstructed floating-point with fraction FRAC, return true
116 *----------------------------------------------------------------------------*/
123         bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
128 /*----------------------------------------------------------------------------
129 | The pattern for a default generated deconstructed floating-point NaN.
130 *----------------------------------------------------------------------------*/
139     frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
143     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
146     /* snan_bit_is_one, set msb-1.  */
147     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
153      * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
155      * do not have floating-point.
159         frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
162         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
178      * in the quad-floating format.  If the low bit is set, assume we
179      * want to set all non-snan bits.
189         .frac_lo = -(p64.frac & 1)
193 /*----------------------------------------------------------------------------
195 | floating-point parts.
196 *----------------------------------------------------------------------------*/
204         frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
205         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
207         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
214     p->frac = parts_silence_nan_frac(p->frac, status);
215     p->cls = float_class_qnan;
220     p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
221     p->cls = float_class_qnan;
224 /*----------------------------------------------------------------------------
225 | The pattern for a default generated extended double-precision NaN.
226 *----------------------------------------------------------------------------*/
234     r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
238     r.low = UINT64_C(0xC000000000000000);
244 /*----------------------------------------------------------------------------
245 | The pattern for a default generated extended double-precision inf.
246 *----------------------------------------------------------------------------*/
258 /*----------------------------------------------------------------------------
259 | Returns 1 if the half-precision floating-point value `a' is a quiet
261 *----------------------------------------------------------------------------*/
278 /*----------------------------------------------------------------------------
281 *----------------------------------------------------------------------------*/
297 /*----------------------------------------------------------------------------
298 | Returns 1 if the half-precision floating-point value `a' is a signaling
300 *----------------------------------------------------------------------------*/
316 /*----------------------------------------------------------------------------
319 *----------------------------------------------------------------------------*/
335 /*----------------------------------------------------------------------------
336 | Returns 1 if the single-precision floating-point value `a' is a quiet
338 *----------------------------------------------------------------------------*/
354 /*----------------------------------------------------------------------------
355 | Returns 1 if the single-precision floating-point value `a' is a signaling
357 *----------------------------------------------------------------------------*/
373 /*----------------------------------------------------------------------------
374 | Select which NaN to propagate for a two-input operation.
376 | algorithm is target-specific.
387 | tie-break rule.
388 *----------------------------------------------------------------------------*/
396      * But if we're not in default-NaN mode then the target must
399     assert(!status->default_nan_mode);
401     switch (status->float_2nan_prop_rule) {
444          * SNaN and a non-NaN => return the SNaN, silenced
445          * QNaN and a non-NaN => return the QNaN
469 /*----------------------------------------------------------------------------
470 | Select which NaN to propagate for a three-input operation.
473 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
474 *----------------------------------------------------------------------------*/
506          * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
529          * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
553      * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
595     /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
648     if (status->use_first_nan) {
679 /*----------------------------------------------------------------------------
680 | Returns 1 if the double-precision floating-point value `a' is a quiet
682 *----------------------------------------------------------------------------*/
699 /*----------------------------------------------------------------------------
700 | Returns 1 if the double-precision floating-point value `a' is a signaling
702 *----------------------------------------------------------------------------*/
719 /*----------------------------------------------------------------------------
720 | Returns 1 if the extended double-precision floating-point value `a' is a
723 *----------------------------------------------------------------------------*/
733             aLow = a.low & ~0x4000000000000000ULL;
736                 && (a.low == aLow);
739                 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
744 /*----------------------------------------------------------------------------
745 | Returns 1 if the extended double-precision floating-point value `a' is a
748 *----------------------------------------------------------------------------*/
757                 && ((a.low << 1) >= 0x8000000000000000ULL);
761             aLow = a.low & ~UINT64_C(0x4000000000000000);
764                 && (a.low == aLow);
769 /*----------------------------------------------------------------------------
770 | Returns a quiet NaN from a signalling NaN for the extended double-precision
772 *----------------------------------------------------------------------------*/
778     a.low |= UINT64_C(0xC000000000000000);
782 /*----------------------------------------------------------------------------
783 | Takes two extended double-precision floating-point values `a' and `b', one
786 *----------------------------------------------------------------------------*/
809     if (status->default_nan_mode) {
813     if (a.low < b.low) {
815     } else if (b.low < a.low) {
834 /*----------------------------------------------------------------------------
835 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
837 *----------------------------------------------------------------------------*/
846                 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
849                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
854 /*----------------------------------------------------------------------------
855 | Returns 1 if the quadruple-precision floating-point value `a' is a
857 *----------------------------------------------------------------------------*/
866                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
869                 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));