Lines Matching full:across

60 persistent memory. The CXL topology may support interleaving across a
88 decisions about how to configure interleave across available CXL
109   may be a mapping to a single Root Port (RP) or across a set of
167   |   |          | |  memory accesses across HB0/HB1  | |          |   |
210     particular interleave setup across the CXL Host Bridges (HB)
213     across HB0 and HB1.
217     a single port or interleave them across multiple ports.
223     CFMW0 to be interleaved across RP0 and RP1, providing 2 way
228     across for example CXL Type3 0 and CXL Type3 2).
229     HDM4 is used to enable system wide 4 way interleave across all
231     requests that HB0 receives from CFMW1 across RP 0 and
252   |   |          | |  memory accesses across HB0/HB1  | |          |   |
336 interleave across 2 CXL host bridges.  Each host bridge has 2 CXL Root Ports, with