system/arm/mps2.rst

1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
19   Cortex-M3 as documented in Arm Application Note AN385
20 ``mps2-an386``
21   Cortex-M4 as documented in Arm Application Note AN386
22 ``mps2-an500``
23   Cortex-M7 as documented in Arm Application Note AN500
24 ``mps2-an505``
25   Cortex-M33 as documented in Arm Application Note AN505
26 ``mps2-an511``
27   Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
28 ``mps2-an521``
29   Dual Cortex-M33 as documented in Arm Application Note AN521
30 ``mps3-an524``
31   Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
32 ``mps3-an547``
33   Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
35 FPGA images using R-profile CPUs:
37 ``mps3-an536``
38   Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
42 - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
45 - AN524 remapping of low memory to either BRAM or to QSPI flash is
47   SCC CFG_REG0 memory-remap bit)
48 - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
51 - QEMU does not model the QSPI flash in MPS3 boards as real QSPI
54 - QEMU does not model the USB controller in MPS3 boards
55 - AN536 does not support runtime control of CPU reset and halt via
57 - AN536 does not support enabling or disabling the flash and ATCM
59 - AN536 does not support setting of the initial vector table
64 - AN536 defaults to only creating a single CPU; this is the equivalent
65   of the way the real FPGA image usually runs with the second Cortex-R52
67   create the second CPU with ``-smp 2``; both CPUs will then start
77 no "CPU1-only UART", the UART numbering remains the same,
80 Machine-specific options
83 The following machine-specific options are supported:
86   Supported for ``mps3-an524`` only.