docs/specs/fsi.rst

5 The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, FSI
8 FSI is a point-to-point two wire interface which is capable of supporting
33    driving CFAM engine accesses into the POWER chip. At the hardware level
34    FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
37 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
40    MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
43 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
44    AST2600. Hardware limitations prevent the OPB from being directly mapped
54 CFAM to be simultaneously driven from multiple FSI links. The modeling is not
58 As for FSI, its symbols and wire-protocol are not modelled at all. This is not
60 space onto the OPB address space - the models follow this directly and map the
63 The following commands start the ``rainier-bmc`` machine with built-in FSI
65 learn more about Aspeed ``rainier-bmc`` machine: (:doc:`../../system/arm/aspeed`)
67 .. code-block:: console
69   qemu-system-arm -M rainier-bmc -nographic \
70   -kernel fitImage-linux.bin \
71   -dtb aspeed-bmc-ibm-rainier.dtb \
72   -initrd obmc-phosphor-initramfs.rootfs.cpio.xz \
73   -drive file=obmc-phosphor-image.rootfs.wic.qcow2,if=sd,index=2 \
74   -append "rootwait console=ttyS4,115200n8 root=PARTLABEL=rofs-a"
78 .. code-block:: console
81   bus: main-system-bus
85       gpio-out "sysbus-irq" 1
113 .. code-block:: console
115   root@p10bmc:~# pdbg -a getcfam 0x0
122    https://github.com/open-power/pdbg