docs/devel/tcg-ops.rst

62    add_i32 t0, t1, t2    /* (t0 <- t1 + t2) */
207      add_i32 t0, t1, t2
256        |   ``TCG_COND_TSTEQ /* t1 & t2 == 0 */``
257        |   ``TCG_COND_TSTNE /* t1 & t2 != 0 */``
264    * - add_i32/i64 *t0*, *t1*, *t2*
266      - | *t0* = *t1* + *t2*
268    * - sub_i32/i64 *t0*, *t1*, *t2*
270      - | *t0* = *t1* - *t2*
276    * - mul_i32/i64 *t0*, *t1*, *t2*
278      - | *t0* = *t1* * *t2*
280    * - div_i32/i64 *t0*, *t1*, *t2*
282      - | *t0* = *t1* / *t2* (signed)
285    * - divu_i32/i64 *t0*, *t1*, *t2*
287      - | *t0* = *t1* / *t2* (unsigned)
290    * - rem_i32/i64 *t0*, *t1*, *t2*
292      - | *t0* = *t1* % *t2* (signed)
295    * - remu_i32/i64 *t0*, *t1*, *t2*
297      - | *t0* = *t1* % *t2* (unsigned)
306    * - and_i32/i64 *t0*, *t1*, *t2*
308      - | *t0* = *t1* & *t2*
310    * - or_i32/i64 *t0*, *t1*, *t2*
312      - | *t0* = *t1* | *t2*
314    * - xor_i32/i64 *t0*, *t1*, *t2*
316      - | *t0* = *t1* ^ *t2*
322    * - andc_i32/i64 *t0*, *t1*, *t2*
324      - | *t0* = *t1* & ~\ *t2*
326    * - eqv_i32/i64 *t0*, *t1*, *t2*
328      - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2*
330    * - nand_i32/i64 *t0*, *t1*, *t2*
332      - | *t0* = ~(*t1* & *t2*)
334    * - nor_i32/i64 *t0*, *t1*, *t2*
336      - | *t0* = ~(*t1* | *t2*)
338    * - orc_i32/i64 *t0*, *t1*, *t2*
340      - | *t0* = *t1* | ~\ *t2*
342    * - clz_i32/i64 *t0*, *t1*, *t2*
344      - | *t0* = *t1* ? clz(*t1*) : *t2*
346    * - ctz_i32/i64 *t0*, *t1*, *t2*
348      - | *t0* = *t1* ? ctz(*t1*) : *t2*
363    * - shl_i32/i64 *t0*, *t1*, *t2*
365      - | *t0* = *t1* << *t2*
366        | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
368    * - shr_i32/i64 *t0*, *t1*, *t2*
370      - | *t0* = *t1* >> *t2* (unsigned)
371        | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
373    * - sar_i32/i64 *t0*, *t1*, *t2*
375      - | *t0* = *t1* >> *t2* (signed)
376        | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
378    * - rotl_i32/i64 *t0*, *t1*, *t2*
380      - | Rotation of *t2* bits to the left
381        | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
383    * - rotr_i32/i64 *t0*, *t1*, *t2*
385      - | Rotation of *t2* bits to the right.
386        | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
440    * - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len*
442      - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*.
449        | For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
452        |     *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00)
472    * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos*
475          of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander
497    * - setcond_i32/i64 *dest*, *t1*, *t2*, *cond*
499      - | *dest* = (*t1* *cond* *t2*)
501        | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
503    * - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond*
505      - | *dest* = -(*t1* *cond* *t2*)
507        | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
533    * - concat_i32_i64 *t0*, *t1*, *t2*
536          from *t2* (32 bit).
538    * - concat32_i64 *t0*, *t1*, *t2*
541          from *t2* (64 bit).
593      - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are
597    * - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
599      - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full
602    * - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
604      - | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
606    * - mulsh_i32/i64 *t0*, *t1*, *t2*
608        muluh_i32/i64 *t0*, *t1*, *t2*
655      - | Similar to setcond, except that the 64-bit values *t1* and *t2* are