docs/devel/loads-stores.rst

9 QEMU internally has multiple families of functions for performing
12 documentation of each API -- for that you should look at the
32  - (empty) : for 32 or 64 bit sizes
33  - ``u`` : unsigned
34  - ``s`` : signed
37  - ``b`` : 8 bits
38  - ``w`` : 16 bits
39  - ``24`` : 24 bits
40  - ``l`` : 32 bits
41  - ``q`` : 64 bits
44  - ``he`` : host endian
45  - ``be`` : big endian
46  - ``le`` : little endian
48 The ``_{endian}`` infix is omitted for target-endian accesses.
51 files which are built per-target.
67  - ``\<ld[us]\?[bwlq]\(_[hbl]e\)\?_p\>``
68  - ``\<st[bwlq]\(_[hbl]e\)\?_p\>``
69  - ``\<st24\(_[hbl]e\)\?_p\>``
70  - ``\<ldn_\([hbl]e\)\?_p\>``
71  - ``\<stn_\([hbl]e\)\?_p\>``
84 requires a "always as non-privileged" access rather than the
113  - ``b`` : 8 bits
114  - ``w`` : 16 bits
115  - ``l`` : 32 bits
116  - ``q`` : 64 bits
119  - (empty) : for target endian, or 8 bit sizes
120  - ``_be`` : big endian
121  - ``_le`` : little endian
124  - ``\<cpu_ld[bwlq]\(_[bl]e\)\?_mmu\>``
125  - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmu\>``
142  - (empty) : for 32 or 64 bit sizes
143  - ``u`` : unsigned
144  - ``s`` : signed
147  - ``b`` : 8 bits
148  - ``w`` : 16 bits
149  - ``l`` : 32 bits
150  - ``q`` : 64 bits
153  - (empty) : for target endian, or 8 bit sizes
154  - ``_be`` : big endian
155  - ``_le`` : little endian
158  - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
159  - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
180  - (empty) : for 32 or 64 bit sizes
181  - ``u`` : unsigned
182  - ``s`` : signed
185  - ``b`` : 8 bits
186  - ``w`` : 16 bits
187  - ``l`` : 32 bits
188  - ``q`` : 64 bits
191  - (empty) : for target endian, or 8 bit sizes
192  - ``_be`` : big endian
193  - ``_le`` : little endian
196  - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data_ra\>``
197  - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data_ra\>``
207 translator has saved all necessary CPU state.  These functions are
209 hook or when you know for certain that the translator had to save all
219  - (empty) : for 32 or 64 bit sizes
220  - ``u`` : unsigned
221  - ``s`` : signed
224  - ``b`` : 8 bits
225  - ``w`` : 16 bits
226  - ``l`` : 32 bits
227  - ``q`` : 64 bits
230  - (empty) : for target endian, or 8 bit sizes
231  - ``_be`` : big endian
232  - ``_le`` : little endian
235  - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data\>``
236  - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data\+\>``
258  - (empty) : for 32 or 64 bit sizes
259  - ``u`` : unsigned
260  - ``s`` : signed
263  - ``b`` : 8 bits
264  - ``w`` : 16 bits
265  - ``l`` : 32 bits
266  - ``q`` : 64 bits
269  - ``\<cpu_ld[us]\?[bwlq]_code\>``
276 called during the translator callback ``translate_insn``.
289  - (empty) : for 32 or 64 bit sizes
290  - ``u`` : unsigned
291  - ``s`` : signed
294  - ``b`` : 8 bits
295  - ``w`` : 16 bits
296  - ``l`` : 32 bits
297  - ``q`` : 64 bits
300  - ``\<translator_ld[us]\?[bwlq]\(_swap\)\?\>``
318  - (empty) : for 32 or 64 bit sizes
319  - ``u`` : unsigned
320  - ``s`` : signed
323  - ``b`` : 8 bits
324  - ``w`` : 16 bits
325  - ``l`` : 32 bits
326  - ``q`` : 64 bits
329  - ``\<helper_ld[us]\?[bwlq]_mmu\>``
330  - ``\<helper_st[bwlq]_mmu\>``
337 way QEMU defines the view of memory that a device or CPU has.
341 Each CPU has an AddressSpace. Some kinds of CPU have more than
344 Devices which can do DMA-type operations should generally have an
346 has all the devices and memory that all CPUs can see. (Some older
350 Functions are provided for doing byte-buffer reads and writes,
351 and also for doing one-data-item loads and stores.
354 transaction attributes, and can check whether the memory transaction
368  - (empty) : for 32 or 64 bit sizes
369  - ``u`` : unsigned
374  - ``b`` : 8 bits
375  - ``w`` : 16 bits
376  - ``l`` : 32 bits
377  - ``q`` : 64 bits
380  - ``le`` : little endian
381  - ``be`` : big endian
386  - ``\<address_space_\(read\|write\|rw\)\>``
387  - ``\<address_space_ldu\?[bwql]\(_[lb]e\)\?\>``
388  - ``\<address_space_st[bwql]\(_[lb]e\)\?\>``
396 CPU to the ROM would be ignored. This is used for non-guest writes
400 device will be silently ignored -- only real RAM and ROM will
404  - ``address_space_write_rom``
411 ``MEMTXATTRS_UNSPECIFIED`` for the transaction attributes, and ignore
412 whether the transaction succeeded or failed.
414 The fact that they ignore whether the transaction succeeded means
417 device doing the access has no way to report such an error.
424  - (empty) : for 32 or 64 bit sizes
425  - ``u`` : unsigned
430  - ``b`` : 8 bits
431  - ``w`` : 16 bits
432  - ``l`` : 32 bits
433  - ``q`` : 64 bits
436  - ``le`` : little endian
437  - ``be`` : big endian
442  - ``\<ldu\?[bwlq]\(_[bl]e\)\?_phys\>``
443  - ``\<st[bwlq]\(_[bl]e\)\?_phys\>``
451 ignore whether the memory transaction succeeded or failed.
466  - ``\<cpu_physical_memory_\(read\|write\|rw\)\>``
501  - ``\<dma_memory_\(read\|write\|rw\)\>``
502  - ``\<ldu\?[bwlq]\(_[bl]e\)\?_dma\>``
503  - ``\<st[bwlq]\(_[bl]e\)\?_dma\>``
524  - (empty) : for 32 or 64 bit sizes
525  - ``u`` : unsigned
530  - ``b`` : 8 bits
531  - ``w`` : 16 bits
532  - ``l`` : 32 bits
533  - ``q`` : 64 bits
536  - ``le`` : little endian
537  - ``be`` : big endian
542  - ``\<pci_dma_\(read\|write\|rw\)\>``
543  - ``\<ldu\?[bwlq]\(_[bl]e\)\?_pci_dma\>``
544  - ``\<st[bwlq]\(_[bl]e\)\?_pci_dma\>``