Lines Matching +full:asi +full:- +full:format
3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
30 #include "disas/dis-asm.h"
33 the opcodes library in sparc-opc.c. If you change anything here, make
36 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
43 returns non-zero.
44 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
45 Don't change this without updating sparc-opc.c. */
62 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
68 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
169 o %asi. (v9)
191 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
192 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
196 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ macro
221 fill-column: 131
222 comment-column: 0
225 /* opcodes/sparc-opc.c */
248 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
357 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
397 'ld' pseudo-op in v9. */
405 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
411 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
418 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
425 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
432 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
440 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
446 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
453 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
460 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
467 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
474 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
578 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
584 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
591 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
597 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
604 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
611 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
617 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
623 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
630 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
670 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
677 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
683 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
710 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
717 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
723 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
730 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
736 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
743 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
763 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
770 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
776 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
803 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
810 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
824 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
831 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
838 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
852 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
857 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6…
865 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
872 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
889 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
897 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
904 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
943 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
946 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
949 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
952 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
957 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v…
964 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
971 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
978 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
985 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
990 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
994 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
998 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, …
1001 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r…
1004 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r…
1007 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* w…
1010 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* w…
1013 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* w…
1017 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r…
1019 …r", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%a…
1020 …F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
1021 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r…
1024 { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1026 { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1028 { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1030 { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1032 { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1034 { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1036 { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1038 { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,…
1040 { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,…
1042 { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,…
1052 …, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1081 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* …
1083 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* …
1085 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }…
1087 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }…
1089 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }…
1114 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,r…
1119 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
1123 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs…
1127 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
1131 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
1134 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,…
1137 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs…
1140 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
1143 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
1146 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6 },
1149 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6 },
1152 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
1156 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
1169 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs…
1172 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,…
1173 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd…
1175 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
1178 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
1182 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6 },
1186 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6 },
1190 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1193 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1196 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1199 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1202 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1205 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1208 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1211 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1215 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1217 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1219 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1225 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELA…
1226 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DE…
1243 a single-line description of each condition value. John Gilmore. */
1245 /* Define branches -- one annulled, one without, etc. */
1457 #define FM_SF 1 /* v9 - values for fpsize */
1617 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6…
1633 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1636 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1640 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1642 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1649 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1653 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1656 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1659 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1663 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd …
1664 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1666 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2…
1828 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1853 /*SLCBCC("cbn", 0), - already defined */
1861 /*SLCBCC("cba", 8), - already defined */
1880 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* …
1881 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sr…
1882 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* …
1883 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sr…
1884 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /…
1885 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /…
1886 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /…
1887 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /…
1993 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2026 for (p = table; p->name; ++p) in lookup_value()
2027 if (value == p->value) in lookup_value()
2028 return p->name; in lookup_value()
2033 /* Handle ASI's. */
2145 /* Return the name for ASI value VALUE or NULL if not found. */
2226 /* opcodes/sparc-dis.c */
2250 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2252 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2275 /* Sign-extend a value which is N bits long. */
2277 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2278 >> ((8 * sizeof (int)) - bits) )
2306 /* "ver" - special cased */
2321 rd and wr insns (-16). */
2336 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2364 #define asi ldst.anasi
2412 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in is_delayed_branch()
2414 const sparc_opcode *opcode = op->opcode; in is_delayed_branch()
2416 if ((opcode->match & insn) == opcode->match in is_delayed_branch()
2417 && (opcode->lose & insn) == 0) in is_delayed_branch()
2418 return opcode->flags & F_DELAYED; in is_delayed_branch()
2468 unsigned long int match0 = op0->match, match1 = op1->match; in compare_opcodes()
2469 unsigned long int lose0 = op0->lose, lose1 = op1->lose; in compare_opcodes()
2477 if (op0->architecture & current_arch_mask) in compare_opcodes()
2479 if (! (op1->architecture & current_arch_mask)) in compare_opcodes()
2480 return -1; in compare_opcodes()
2484 if (op1->architecture & current_arch_mask) in compare_opcodes()
2486 else if (op0->architecture != op1->architecture) in compare_opcodes()
2487 return op0->architecture - op1->architecture; in compare_opcodes()
2496 /* xgettext:c-format */ in compare_opcodes()
2497 "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", in compare_opcodes()
2498 op0->name, match0, lose0); in compare_opcodes()
2499 op0->lose &= ~op0->match; in compare_opcodes()
2500 lose0 = op0->lose; in compare_opcodes()
2507 /* xgettext:c-format */ in compare_opcodes()
2508 "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", in compare_opcodes()
2509 op1->name, match1, lose1); in compare_opcodes()
2510 op1->lose &= ~op1->match; in compare_opcodes()
2511 lose1 = op1->lose; in compare_opcodes()
2523 return x1 - x0; in compare_opcodes()
2533 return x1 - x0; in compare_opcodes()
2541 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); in compare_opcodes()
2550 i = strcmp (op0->name, op1->name); in compare_opcodes()
2553 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ in compare_opcodes()
2557 /* xgettext:c-format */ in compare_opcodes()
2558 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n", in compare_opcodes()
2559 op0->name, op1->name); in compare_opcodes()
2564 int length_diff = strlen (op0->args) - strlen (op1->args); in compare_opcodes()
2573 char *p0 = (char *) strchr (op0->args, '+'); in compare_opcodes()
2574 char *p1 = (char *) strchr (op1->args, '+'); in compare_opcodes()
2580 so the following [-1]'s are valid. */ in compare_opcodes()
2581 if (p0[-1] == 'i' && p1[1] == 'i') in compare_opcodes()
2584 if (p0[1] == 'i' && p1[-1] == 'i') in compare_opcodes()
2586 return -1; in compare_opcodes()
2592 int i0 = strncmp (op0->args, "i,1", 3) == 0; in compare_opcodes()
2593 int i1 = strncmp (op1->args, "i,1", 3) == 0; in compare_opcodes()
2596 return i0 - i1; in compare_opcodes()
2627 for (i = num_opcodes - 1; i >= 0; --i) in build_hash_table()
2629 int hash = HASH_INSN (opcode_table[i]->match); in build_hash_table()
2632 h->next = hash_table[hash]; in build_hash_table()
2633 h->opcode = opcode_table[i]; in build_hash_table()
2658 /* Print one instruction from MEMADDR on INFO->STREAM.
2669 FILE *stream = info->stream; in print_insn_sparc()
2680 || info->mach != current_mach) in print_insn_sparc()
2684 current_arch_mask = compute_arch_mask (info->mach); in print_insn_sparc()
2696 current_mach = info->mach; in print_insn_sparc()
2702 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); in print_insn_sparc()
2706 (*info->memory_error_func) (status, memaddr, info); in print_insn_sparc()
2707 return -1; in print_insn_sparc()
2712 are always big-endian even when the machine is in little-endian mode. */ in print_insn_sparc()
2713 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) in print_insn_sparc()
2720 info->insn_info_valid = 1; /* We do return this info. */ in print_insn_sparc()
2721 info->insn_type = dis_nonbranch; /* Assume non branch insn. */ in print_insn_sparc()
2722 info->branch_delay_insns = 0; /* Assume no delay. */ in print_insn_sparc()
2723 info->target = 0; /* Assume no target known. */ in print_insn_sparc()
2725 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in print_insn_sparc()
2727 const sparc_opcode *opcode = op->opcode; in print_insn_sparc()
2730 if (! (opcode->architecture & current_arch_mask)) in print_insn_sparc()
2733 if ((opcode->match & insn) == opcode->match in print_insn_sparc()
2734 && (opcode->lose & insn) == 0) in print_insn_sparc()
2750 if (opcode->match == 0x80102000) /* or */ in print_insn_sparc()
2752 if (opcode->match == 0x80002000) /* add */ in print_insn_sparc()
2756 && strchr (opcode->args, 'r') != NULL) in print_insn_sparc()
2757 /* Can't do simple format if source and dest are different. */ in print_insn_sparc()
2760 && strchr (opcode->args, 'O') != NULL) in print_insn_sparc()
2761 /* Can't do simple format if source and dest are different. */ in print_insn_sparc()
2764 (*info->fprintf_func) (stream, "%s", opcode->name); in print_insn_sparc()
2769 if (opcode->args[0] != ',') in print_insn_sparc()
2770 (*info->fprintf_func) (stream, " "); in print_insn_sparc()
2772 for (s = opcode->args; *s != '\0'; ++s) in print_insn_sparc()
2776 (*info->fprintf_func) (stream, ","); in print_insn_sparc()
2781 (*info->fprintf_func) (stream, "a"); in print_insn_sparc()
2786 (*info->fprintf_func) (stream, "pn"); in print_insn_sparc()
2791 (*info->fprintf_func) (stream, "pt"); in print_insn_sparc()
2800 (*info->fprintf_func) (stream, " "); in print_insn_sparc()
2809 (*info->fprintf_func) (stream, "%c", *s); in print_insn_sparc()
2813 (*info->fprintf_func) (stream, "0"); in print_insn_sparc()
2816 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) in print_insn_sparc()
2832 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) in print_insn_sparc()
2833 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) <… in print_insn_sparc()
2860 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) in print_insn_sparc()
2875 (*info->fprintf_func) (stream, "%%hi(%#x)", in print_insn_sparc()
2904 (*info->fprintf_func) (stream, "%d", imm); in print_insn_sparc()
2906 (*info->fprintf_func) (stream, "%#x", imm); in print_insn_sparc()
2916 (info->fprintf_func) (stream, "%d", imm); in print_insn_sparc()
2918 (info->fprintf_func) (stream, "%#x", (unsigned) imm); in print_insn_sparc()
2923 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); in print_insn_sparc()
2933 (info->fprintf_func) (stream, "0"); in print_insn_sparc()
2940 (info->fprintf_func) (stream, "|"); in print_insn_sparc()
2942 (info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
2951 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; in print_insn_sparc()
2952 (*info->print_address_func) (info->target, info); in print_insn_sparc()
2956 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; in print_insn_sparc()
2957 (*info->print_address_func) (info->target, info); in print_insn_sparc()
2964 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); in print_insn_sparc()
2968 (*info->fprintf_func) (stream, "%%icc"); in print_insn_sparc()
2972 (*info->fprintf_func) (stream, "%%xcc"); in print_insn_sparc()
2976 (*info->fprintf_func) (stream, "%%ccr"); in print_insn_sparc()
2980 (*info->fprintf_func) (stream, "%%fprs"); in print_insn_sparc()
2984 (*info->fprintf_func) (stream, "%%asi"); in print_insn_sparc()
2988 (*info->fprintf_func) (stream, "%%tick"); in print_insn_sparc()
2992 (*info->fprintf_func) (stream, "%%pc"); in print_insn_sparc()
2997 (*info->fprintf_func) (stream, "%%ver"); in print_insn_sparc()
2999 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3002 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3007 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3010 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3015 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3018 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3023 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3026 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3031 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3033 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3034 v9a_asr_reg_names[X_RS1 (insn)-16]); in print_insn_sparc()
3039 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3041 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3042 v9a_asr_reg_names[X_RD (insn)-16]); in print_insn_sparc()
3050 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3052 (*info->fprintf_func) (stream, "%ld", X_RD (insn)); in print_insn_sparc()
3057 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); in print_insn_sparc()
3061 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); in print_insn_sparc()
3065 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; in print_insn_sparc()
3066 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3070 (*info->fprintf_func) in print_insn_sparc()
3075 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; in print_insn_sparc()
3076 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3083 if ((info->mach == bfd_mach_sparc_v8plusa) || in print_insn_sparc()
3084 ((info->mach >= bfd_mach_sparc_v9) && in print_insn_sparc()
3085 (info->mach <= bfd_mach_sparc_v9b))) in print_insn_sparc()
3091 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3093 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); in print_insn_sparc()
3098 (*info->fprintf_func) (stream, "%%csr"); in print_insn_sparc()
3102 (*info->fprintf_func) (stream, "%%fsr"); in print_insn_sparc()
3106 (*info->fprintf_func) (stream, "%%psr"); in print_insn_sparc()
3110 (*info->fprintf_func) (stream, "%%fq"); in print_insn_sparc()
3114 (*info->fprintf_func) (stream, "%%cq"); in print_insn_sparc()
3118 (*info->fprintf_func) (stream, "%%tbr"); in print_insn_sparc()
3122 (*info->fprintf_func) (stream, "%%wim"); in print_insn_sparc()
3126 (*info->fprintf_func) (stream, "%ld", in print_insn_sparc()
3132 (*info->fprintf_func) (stream, "%%y"); in print_insn_sparc()
3142 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3144 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); in print_insn_sparc()
3164 (*info->read_memory_func) in print_insn_sparc()
3165 (memaddr - 4, buffer, sizeof (buffer), info); in print_insn_sparc()
3184 errcode = (*info->read_memory_func) in print_insn_sparc()
3185 (memaddr - 8, buffer, sizeof (buffer), info); in print_insn_sparc()
3201 (*info->fprintf_func) (stream, "\t! "); in print_insn_sparc()
3202 info->target = in print_insn_sparc()
3206 info->target += X_SIMM (insn, 13); in print_insn_sparc()
3208 info->target |= X_SIMM (insn, 13); in print_insn_sparc()
3209 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3210 info->insn_type = dis_dref; in print_insn_sparc()
3211 info->data_size = 4; /* FIXME!!! */ in print_insn_sparc()
3216 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) in print_insn_sparc()
3218 /* FIXME -- check is_annulled flag. */ in print_insn_sparc()
3219 if (opcode->flags & F_UNBR) in print_insn_sparc()
3220 info->insn_type = dis_branch; in print_insn_sparc()
3221 if (opcode->flags & F_CONDBR) in print_insn_sparc()
3222 info->insn_type = dis_condbranch; in print_insn_sparc()
3223 if (opcode->flags & F_JSR) in print_insn_sparc()
3224 info->insn_type = dis_jsr; in print_insn_sparc()
3225 if (opcode->flags & F_DELAYED) in print_insn_sparc()
3226 info->branch_delay_insns = 1; in print_insn_sparc()
3233 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ in print_insn_sparc()
3234 (*info->fprintf_func) (stream, ".long %#08lx", insn); in print_insn_sparc()