Lines Matching +full:se +full:- +full:neg
19 #include "disas/dis-asm.h"
212 #define arch_op32 0x00100000 /* This is a 32-bit opcode. */
216 #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */
263 the tools to continue to function in most cases - there may
273 .------------'|`--------------------.
275 SH-DSP SH3-nommu SH2E
276 | |`--------. |
278 | SH3 SH4-nommu-nofpu |
280 | .------------'|`----------+---------. |
282 | | .-------' |
284 SH3-dsp SH4-nofpu SH3E
285 | |`--------------------. |
287 | SH4A-nofpu SH4
288 | .------------' `--------------------. |
290 SH4AL-dsp SH4A
514 /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4},…
533 /* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh…
542 /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6},…
561 /* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh…
568 /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5},…
589 /* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh…
613 /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch…
713 /* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_s…
715 /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_…
717 /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_…
719 /* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_s…
721 /* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_s…
723 /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_…
725 /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_…
727 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_…
729 /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_…
731 /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_…
733 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3},…
757 /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch…
759 /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch…
761 /* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_s…
763 /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_…
765 /* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh…
767 /* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh…
769 /* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh…
771 /* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh…
773 /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh…
775 /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch…
777 /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, ar…
823 /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_…
831 /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_…
839 /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_…
847 /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_…
899 /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_…
1027 /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, …
1028 /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}…
1042 /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HE…
1058 /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_…
1118 …/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX…
1120 …/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX…
1166 fprintf_fn (stream, "%s\t", op->name); in print_movxy()
1169 switch (op->arg[n]) in print_movxy()
1238 fprintf_function fprintf_fn = info->fprintf_func; in print_insn_ddt()
1239 void *stream = info->stream; in print_insn_ddt()
1246 and we got a non-nop, emit a tab. */ in print_insn_ddt()
1253 if (info->mach != bfd_mach_sh_dsp in print_insn_ddt()
1254 && info->mach != bfd_mach_sh3_dsp) in print_insn_ddt()
1262 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) in print_insn_ddt()
1264 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) in print_insn_ddt()
1275 while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) in print_insn_ddt()
1276 || op->nibbles[3] != (unsigned) (insn & 0xf)) in print_insn_ddt()
1296 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) in print_insn_ddt()
1298 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) in print_insn_ddt()
1304 for (opx = first_movx; opx->nibbles[2] != insn_x;) in print_insn_ddt()
1314 for (opy = first_movy; opy->nibbles[2] != insn_y;) in print_insn_ddt()
1368 fprintf_function fprintf_fn = info->fprintf_func; in print_insn_ppi()
1369 void *stream = info->stream; in print_insn_ppi()
1399 && info->mach != bfd_mach_sh_dsp in print_insn_ppi()
1400 && info->mach != bfd_mach_sh3_dsp) in print_insn_ppi()
1431 nib3 -= 1; in print_insn_ppi()
1435 nib3 -= 2; in print_insn_ppi()
1442 for (op = sh_table; op->name; op++) in print_insn_ppi()
1444 if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) in print_insn_ppi()
1445 && op->nibbles[2] == nib2 in print_insn_ppi()
1446 && op->nibbles[3] == nib3) in print_insn_ppi()
1450 switch (op->nibbles[4]) in print_insn_ppi()
1473 fprintf_fn (stream, "%s%s\t", dc, op->name); in print_insn_ppi()
1474 for (n = 0; n < 3 && op->arg[n] != A_END; n++) in print_insn_ppi()
1476 if (n && op->arg[1] != A_END) in print_insn_ppi()
1478 switch (op->arg[n]) in print_insn_ppi()
1511 fprintf_function fprintf_fn = info->fprintf_func; in print_insn_sh()
1512 void *stream = info->stream; in print_insn_sh()
1521 switch (info->mach) in print_insn_sh()
1532 if (status != -2) in print_insn_sh()
1541 return -1; in print_insn_sh()
1544 status = info->read_memory_func (memaddr, insn, 2, info); in print_insn_sh()
1548 info->memory_error_func (status, memaddr, info); in print_insn_sh()
1549 return -1; in print_insn_sh()
1552 if (info->endian == BFD_ENDIAN_LITTLE) in print_insn_sh()
1568 status = info->read_memory_func (memaddr + 2, insn + 2, 2, info); in print_insn_sh()
1575 if (info->endian == BFD_ENDIAN_LITTLE) in print_insn_sh()
1600 status = info->read_memory_func (memaddr + 2, insn, 2, info); in print_insn_sh()
1604 info->memory_error_func (status, memaddr + 2, info); in print_insn_sh()
1605 return -1; in print_insn_sh()
1608 if (info->endian == BFD_ENDIAN_LITTLE) in print_insn_sh()
1620 for (op = sh_table; op->name; op++) in print_insn_sh()
1631 int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4; in print_insn_sh()
1634 && SH_MERGE_ARCH_SET (op->arch, arch_op32)) in print_insn_sh()
1637 if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch)) in print_insn_sh()
1641 int i = op->nibbles[n]; in print_insn_sh()
1712 imm -= 0x100000; in print_insn_sh()
1719 imm -= 0x10000000; in print_insn_sh()
1739 imm -= 0x100; in print_insn_sh()
1780 /* sh-dsp: single data transfer. */ in print_insn_sh()
1800 && ((op->arg[0] == DX_REG_M && (rm & 1) != 0) in print_insn_sh()
1801 || (op->arg[1] == DX_REG_N && (rn & 1) != 0))) in print_insn_sh()
1804 fprintf_fn (stream, "%s\t", op->name); in print_insn_sh()
1806 for (n = 0; n < 3 && op->arg[n] != A_END; n++) in print_insn_sh()
1808 if (n && op->arg[1] != A_END) in print_insn_sh()
1810 switch (op->arg[n]) in print_insn_sh()
1827 fprintf_fn (stream, "@-r%d", rn); in print_insn_sh()
1846 fprintf_fn (stream, "@-r%d", rm); in print_insn_sh()
1860 (*info->print_address_func) (disp_pc_addr, info); in print_insn_sh()
1881 fprintf_fn (stream, "@-r15"); in print_insn_sh()
1891 (*info->print_address_func) (addr, info); in print_insn_sh()
2011 if (!(info->flags & 1) in print_insn_sh()
2012 && (op->name[0] == 'j' in print_insn_sh()
2013 || (op->name[0] == 'b' in print_insn_sh()
2014 && (op->name[1] == 'r' in print_insn_sh()
2015 || op->name[1] == 's')) in print_insn_sh()
2016 || (op->name[0] == 'r' && op->name[1] == 't') in print_insn_sh()
2017 || (op->name[0] == 'b' && op->name[2] == '.'))) in print_insn_sh()
2019 info->flags |= 1; in print_insn_sh()
2022 info->flags &= ~1; in print_insn_sh()
2028 if (disp_pc && strcmp (op->name, "mova") != 0) in print_insn_sh()
2037 status = info->read_memory_func (disp_pc_addr, bytes, size, info); in print_insn_sh()
2044 if (info->endian == BFD_ENDIAN_LITTLE) in print_insn_sh()
2051 if (info->endian == BFD_ENDIAN_LITTLE) in print_insn_sh()
2056 if ((*info->symbol_at_address_func) (val, info)) in print_insn_sh()
2059 (*info->print_address_func) (val, info); in print_insn_sh()
2066 return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2; in print_insn_sh()