qemu/disas/alpha.c

320 #define ZA		(FC + 1)  macro
322 #define ZB		(ZA + 1)
651 #define ARG_FPZ1		{ ZA, FB, DFC1 }
656 #define ARG_OPRZ1		{ ZA, RB, DRC1 }
657 #define ARG_OPRLZ1		{ ZA, LIT, RC }
729 			MEM_MASK, BASE, { ZA } },		/* pseudo */
801   { "nop",		OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
802   { "clr",		OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
803   { "mov",		OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
805   { "mov",		OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
1258   { "fnop",		FP(0x17,0x020), BASE, { ZA, ZB, ZC } },	/* pseudo */
1259   { "fclr",		FP(0x17,0x020), BASE, { ZA, ZB, FC } },	/* pseudo */
1283   { "fetch",		MFC(0x18,0x8000), BASE, { ZA, PRB } },
1284   { "fetch_m",		MFC(0x18,0xA000), BASE, { ZA, PRB } },
1287   { "ecb",		MFC(0x18,0xE800), BASE, { ZA, PRB } },	/* ev56 una */
1289   { "wh64",		MFC(0x18,0xF800), BASE, { ZA, PRB } },	/* ev56 una */
1290   { "wh64en",		MFC(0x18,0xFC00), BASE, { ZA, PRB } },	/* ev7 una */
1305 			BASE, { ZA, CPRB } },
1553   { "hw_mtpr",		OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1565   { "hw_jmp", 		EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1566   { "hw_jsr", 		EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1567   { "hw_ret", 		EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1568   { "hw_jcr", 		EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1569   { "hw_coroutine",	EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1570   { "hw_jmp/stall",	EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1571   { "hw_jsr/stall", 	EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1572   { "hw_ret/stall",	EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1573   { "hw_jcr/stall", 	EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1574   { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1716   { "br",		BRA(0x30), BASE, { ZA, BDISP } },	/* pseudo */