89     uint64_t l2_misses;  member
114 static uint64_t l2_misses;  variable
423         __atomic_fetch_add(&insn->l2_misses, 1, __ATOMIC_SEQ_CST);  in vcpu_mem_access()
458         __atomic_fetch_add(&insn->l2_misses, 1, __ATOMIC_SEQ_CST);  in vcpu_insn_exec()
541                               uint64_t l2_access, uint64_t l2_misses)  in append_stats_line()  argument
555     if (l2_access && l2_misses) {  in append_stats_line()
556         double l2_miss_rate =  ((double) l2_misses) / (l2_access) * 100.0;  in append_stats_line()
560                                l2_misses,  in append_stats_line()
579             l2_misses += l2_ucaches[i]->misses;  in sum_stats()
606     return insn_a->l2_misses < insn_b->l2_misses ? 1 : -1;  in l2_cmp()
640                 l2_cache ? l2_mem_accesses : 0, l2_cache ? l2_misses : 0);  in log_stats()
695                                insn->l2_misses, insn->disas_str);  in log_top_insns()