perf/tests/pmu-events.c

34 	const char *alias_long_desc;  member
54 	.alias_long_desc = "L1 BTB Correction",
66 	.alias_long_desc = "L2 BTB Correction",
78 	.alias_long_desc = "Number of segment register loads",
90 	.alias_long_desc = "Memory cluster signals to block micro-op dispatch for any reason",
102 	.alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
115 	.alias_long_desc = "Attributable Level 3 cache access, read",
138 	.alias_long_desc = "DDRC write commands",
152 ….alias_long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor co…
166 	.alias_long_desc = "UNC_CBO_HYPHEN",
180 	.alias_long_desc = "UNC_CBO_TWO_HYPH",
194 	.alias_long_desc = "Total read hits",
208 	.alias_long_desc = "Total cache misses",
222 	.alias_long_desc = "Total cache hits",
247 	.alias_long_desc = "ddr write-cycles event",
261 	.alias_long_desc = "ccn read-cycles event",
369 	if (!is_same(alias->long_desc, test_event->alias_long_desc)) {  in compare_alias_to_test_event()
372 			  test_event->alias_long_desc);  in compare_alias_to_test_event()
388 	if (!is_same(alias->long_desc, test_event->alias_long_desc)) {  in compare_alias_to_test_event()
390 			  pmu_name, alias->str, test_event->alias_long_desc);  in compare_alias_to_test_event()