x86/tigerlake/pipeline.json

7 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
117         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
135 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
139 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
166 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
190 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
341 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
354         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
357 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
362         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
366 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
387 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
391 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
425 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
457 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
466 …"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream…
475 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
483 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
498         "BriefDescription": "Self-modifying code (SMC) detected.",
501 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
525 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
540 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
551 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
556 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
559 …-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued…
567 …t were issued but not retired from the speculative path as well as the out-of-order engine recover…
572 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
574 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
579 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
582 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
598 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
606 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
614 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
622 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
630 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
638 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
646 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
659 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
663 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
668 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
672 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
677 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
681 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
686 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
690 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
695         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
699         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
704         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
708         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
713         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
717         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
722         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
726         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
741         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
774 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
777 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…