x86/skylake/frontend.json

3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
88         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
94 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
99 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
109 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
115 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
120 …after an interval where the front-end delivered no uops for a period of 2 cycles which was not int…
130 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
140 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
146 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
151 … an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was no…
161 … an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was no…
171 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
177 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
182 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
192 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
202 …fter an interval where the front-end delivered no uops for a period of 64 cycles which was not int…
212 …after an interval where the front-end delivered no uops for a period of 8 cycles which was not int…
218 …ctions that are delivered to the back-end after a front-end stall of at least 8 cycles. During thi…
242 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
249 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
405 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
414 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
432 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
437         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
441         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
446         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
450         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",