x86/sapphirerapids/pipeline.json

6 …"PublicDescription": "Number of AMX-based retired arithmetic bfloat16 (BF16) floating-point operat…
11         "BriefDescription": "AMX retired arithmetic integer 8-bit operations.",
14 …"PublicDescription": "Number of AMX-based retired arithmetic integer operations of 8-bit width sou…
32 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
168         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
186 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
190 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
217 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
222 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
225 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
230 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
233 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
281 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
428         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
431 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
436         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
440 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
459         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
462 …ons Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Cou…
470 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
520 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
539         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
542 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
547         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
550 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
610 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
619 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
628 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
636 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
651         "BriefDescription": "Self-modifying code (SMC) detected.",
654 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
678 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
690 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
693 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
701 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
709 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
721 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
723 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
728 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
731 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
807 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
811 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
816 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
820 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
825 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
829 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
834 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
838 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
843         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
847         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
852         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
856         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
861         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
865         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
870         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
874         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
899         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
934 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …